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hv: vpci: handle the quirk part for pass through pci device cfg access in dm
There're some PCI devices need special handler for vendor-specical feature or capability CFG access. The Intel GPU is one of them. In order to keep the ACRN-HV clean, we want to throw the qurik part of PCI CFG asccess to DM to handle. To achieve this, we implement per-device policy base on whether it needs quirk handler for a VM: each device could configure as "quirk pass through device" or not. For a "quirk pass through device", we will handle the general part in HV and the quirk part in DM. For a non "quirk pass through device", we will handle all the part in HV. Tracked-On: #4371 Signed-off-by: Li Fei1 <fei1.li@intel.com>
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@@ -104,6 +104,8 @@ struct pci_vdev {
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union pci_cfgdata cfgdata;
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uint32_t flags;
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/* The bar info of the virtual PCI device. */
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uint32_t nr_bars; /* 6 for normal device, 2 for bridge, 1 for cardbus */
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struct pci_vbar vbars[PCI_BAR_COUNT];
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@@ -186,10 +186,6 @@
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#define HOST_BRIDGE_BDF 0U
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#define PCI_STD_NUM_BARS 6U
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/* Graphics definitions */
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#define PCIR_BDSM 0x5CU /* BDSM graphics base data of stolen memory register */
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#define PCIR_ASLS_CTL 0xFCU /* Opregion start addr register */
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union pci_bdf {
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uint16_t value;
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struct {
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@@ -255,11 +251,6 @@ struct pci_cfg_ops {
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void (*pci_write_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
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};
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static inline bool is_gvtd(union pci_bdf bdf)
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{
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return (bdf.value == CONFIG_GPU_SBDF);
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}
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static inline uint32_t pci_bar_offset(uint32_t idx)
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{
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return PCIR_BARS + (idx << 2U);
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@@ -272,8 +272,9 @@ struct hc_ptdev_irq {
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* the parameter for HC_ASSIGN_PCIDEV or HC_DEASSIGN_PCIDEV hypercall
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*/
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struct acrn_assign_pcidev {
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/** reversed for externed compatibility */
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uint32_t rsvd1;
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#define QUIRK_PTDEV (1U << 0) /* We will only handle general part in HV, others in DM */
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/** the type of the the pass-through PCI device */
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uint32_t type;
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/** virtual BDF# of the pass-through PCI device */
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uint16_t virt_bdf;
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