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hv: vpci: handle the quirk part for pass through pci device cfg access in dm

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There're some PCI devices need special handler for vendor-specical feature or
capability CFG access. The Intel GPU is one of them. In order to keep the ACRN-HV
clean, we want to throw the qurik part of PCI CFG asccess to DM to handle.

To achieve this, we implement per-device policy base on whether it needs quirk handler
for a VM: each device could configure as "quirk pass through device" or not. For a
"quirk pass through device", we will handle the general part in HV and the quirk part
in DM. For a non "quirk pass through device",  we will handle all the part in HV.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1
2020-03-13 11:44:51 +08:00
committed by wenlingz
parent e5c7a96513
commit e99ddf28c3
7 changed files with 75 additions and 36 deletions
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9
hypervisor/include/hw/pci.h
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@@ -186,10 +186,6 @@
#define HOST_BRIDGE_BDF 0U
#define PCI_STD_NUM_BARS 6U
/* Graphics definitions */
#define PCIR_BDSM 0x5CU /* BDSM graphics base data of stolen memory register */
#define PCIR_ASLS_CTL 0xFCU /* Opregion start addr register */
union pci_bdf {
uint16_t value;
struct {
@@ -255,11 +251,6 @@ struct pci_cfg_ops {
void (*pci_write_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
};
static inline bool is_gvtd(union pci_bdf bdf)
{
return (bdf.value == CONFIG_GPU_SBDF);
}
static inline uint32_t pci_bar_offset(uint32_t idx)
{
return PCIR_BARS + (idx << 2U);