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HV: enumerate capability of #AC for Splitlock Access

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When the destination of an atomic memory operation located in 2
cache lines, it is called a Splitlock Access. LOCK# bus signal is
asserted for splitlock access which may lead to long latency. #AC
for Splitlock Access is a CPU feature, it allows rise alignment
check exception #AC(0) instead of asserting LOCK#, that is helpful
to detect Splitlock Access.

This feature is enumerated by MSR(0xcf) IA32_CORE_CAPABILITIES[bit5]
Add helper function:
    bool has_core_cap(uint32_t bitmask)

Tracked-On: #4496
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
yuhong.tao@intel.com
2020-03-16 21:41:23 +08:00
committed by wenlingz
parent decd89e48d
commit ea1bce0cbf
4 changed files with 17 additions and 0 deletions
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14
hypervisor/arch/x86/cpu_caps.c
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@@ -37,6 +37,7 @@ static struct cpu_capability {
uint32_t vmx_ept;
uint32_t vmx_vpid;
uint32_t core_caps; /* value of MSR_IA32_CORE_CAPABLITIES */
} cpu_caps;
static struct cpuinfo_x86 boot_cpu_data;
@@ -124,6 +125,11 @@ bool is_apl_platform(void)
return ret;
}
bool has_core_cap(uint32_t bit_mask)
{
return ((cpu_caps.core_caps & bit_mask) != 0U);
}
static void detect_ept_cap(void)
{
uint64_t msr_val;
@@ -216,12 +222,20 @@ static void detect_xsave_cap(void)
&boot_cpu_data.cpuid_leaves[FEAT_D_1_EDX]);
}
static void detect_core_caps(void)
{
if (pcpu_has_cap(X86_FEATURE_CORE_CAP)) {
cpu_caps.core_caps = (uint32_t)msr_read(MSR_IA32_CORE_CAPABILITIES);
}
}
static void detect_pcpu_cap(void)
{
detect_apicv_cap();
detect_ept_cap();
detect_vmx_mmu_cap();
detect_xsave_cap();
detect_core_caps();
}
static uint64_t get_address_mask(uint8_t limit)