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HV: enumerate capability of #AC for Splitlock Access

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When the destination of an atomic memory operation located in 2
cache lines, it is called a Splitlock Access. LOCK# bus signal is
asserted for splitlock access which may lead to long latency. #AC
for Splitlock Access is a CPU feature, it allows rise alignment
check exception #AC(0) instead of asserting LOCK#, that is helpful
to detect Splitlock Access.

This feature is enumerated by MSR(0xcf) IA32_CORE_CAPABILITIES[bit5]
Add helper function:
    bool has_core_cap(uint32_t bitmask)

Tracked-On: #4496
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
yuhong.tao@intel.com
2020-03-16 21:41:23 +08:00
committed by wenlingz
parent decd89e48d
commit ea1bce0cbf
4 changed files with 17 additions and 0 deletions
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1
hypervisor/include/arch/x86/cpu_caps.h
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@@ -49,6 +49,7 @@ bool pcpu_has_cap(uint32_t bit);
bool pcpu_has_vmx_ept_cap(uint32_t bit_mask);
bool pcpu_has_vmx_vpid_cap(uint32_t bit_mask);
bool is_apl_platform(void);
bool has_core_cap(uint32_t bit_mask);
void init_pcpu_capabilities(void);
void init_pcpu_model_name(void);
int32_t detect_hardware_support(void);

1
hypervisor/include/arch/x86/cpufeatures.h
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@@ -84,6 +84,7 @@
#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5U) + 27U)
#define X86_FEATURE_L1D_FLUSH ((FEAT_7_0_EDX << 5U) + 28U)
#define X86_FEATURE_ARCH_CAP ((FEAT_7_0_EDX << 5U) + 29U)
#define X86_FEATURE_CORE_CAP ((FEAT_7_0_EDX << 5U) + 30U)
#define X86_FEATURE_SSBD ((FEAT_7_0_EDX << 5U) + 31U)
/* Intel-defined CPU features, CPUID level 0x80000001 (EDX)*/

1
hypervisor/include/arch/x86/msr.h
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@@ -40,6 +40,7 @@
#define MSR_IA32_PMC5 0x000000C6U
#define MSR_IA32_PMC6 0x000000C7U
#define MSR_IA32_PMC7 0x000000C8U
#define MSR_IA32_CORE_CAPABILITIES 0x000000CFU
/* Max. qualified performance clock counter */
#define MSR_IA32_MPERF 0x000000E7U
/* Actual performance clock counter */