HV: remove multiple exit/return in routines in the file of vlapic.c

To meet MISRA, remove few return in routines of vlapic.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Chaohong guo 2018-12-29 11:09:54 +08:00 committed by wenlingz
parent 8e00180c9f
commit eaa0e307b7

View File

@ -111,17 +111,23 @@ static uint16_t vm_apicid2vcpu_id(struct acrn_vm *vm, uint8_t lapicid)
{ {
uint16_t i; uint16_t i;
struct acrn_vcpu *vcpu; struct acrn_vcpu *vcpu;
uint16_t cpu_id = INVALID_CPU_ID;
foreach_vcpu(i, vm, vcpu) { foreach_vcpu(i, vm, vcpu) {
const struct acrn_vlapic *vlapic = vcpu_vlapic(vcpu); const struct acrn_vlapic *vlapic = vcpu_vlapic(vcpu);
if (vlapic_get_apicid(vlapic) == lapicid) { if (vlapic_get_apicid(vlapic) == lapicid) {
return vcpu->vcpu_id; cpu_id = vcpu->vcpu_id;
break;
} }
} }
if (cpu_id == INVALID_CPU_ID) {
cpu_id = get_pcpu_nums();
pr_err("%s: bad lapicid %hhu", __func__, lapicid); pr_err("%s: bad lapicid %hhu", __func__, lapicid);
}
return cpu_id;
return get_pcpu_nums();
} }
/* /*
@ -626,10 +632,12 @@ vlapic_get_lvtptr(struct acrn_vlapic *vlapic, uint32_t offset)
{ {
struct lapic_regs *lapic = &(vlapic->apic_page); struct lapic_regs *lapic = &(vlapic->apic_page);
uint32_t i; uint32_t i;
uint32_t *lvt_ptr;
switch (offset) { switch (offset) {
case APIC_OFFSET_CMCI_LVT: case APIC_OFFSET_CMCI_LVT:
return &lapic->lvt_cmci.v; lvt_ptr = &lapic->lvt_cmci.v;
break;
default: default:
/* /*
* The function caller could guarantee the pre condition. * The function caller could guarantee the pre condition.
@ -637,8 +645,10 @@ vlapic_get_lvtptr(struct acrn_vlapic *vlapic, uint32_t offset)
* could be handled here. * could be handled here.
*/ */
i = lvt_off_to_idx(offset); i = lvt_off_to_idx(offset);
return &(lapic->lvt[i].v); lvt_ptr = &(lapic->lvt[i].v);
break;
} }
return lvt_ptr;
} }
static inline uint32_t static inline uint32_t
@ -656,6 +666,7 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
{ {
uint32_t *lvtptr, mask, val, idx; uint32_t *lvtptr, mask, val, idx;
struct lapic_regs *lapic; struct lapic_regs *lapic;
bool error = false;
lapic = &(vlapic->apic_page); lapic = &(vlapic->apic_page);
lvtptr = vlapic_get_lvtptr(vlapic, offset); lvtptr = vlapic_get_lvtptr(vlapic, offset);
@ -695,7 +706,7 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
"vpic wire mode -> LAPIC"); "vpic wire mode -> LAPIC");
} else { } else {
pr_err("WARNING:invalid vpic wire mode change"); pr_err("WARNING:invalid vpic wire mode change");
return; error = true;
} }
/* unmask -> mask: only from the vlapic LINT0-ExtINT enabled */ /* unmask -> mask: only from the vlapic LINT0-ExtINT enabled */
} else if (((last & APIC_LVT_M) == 0U) && ((val & APIC_LVT_M) != 0U)) { } else if (((last & APIC_LVT_M) == 0U) && ((val & APIC_LVT_M) != 0U)) {
@ -713,10 +724,12 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
/* No action required. */ /* No action required. */
} }
if (error == false) {
*lvtptr = val; *lvtptr = val;
idx = lvt_off_to_idx(offset); idx = lvt_off_to_idx(offset);
atomic_store32(&vlapic->lvt_last[idx], val); atomic_store32(&vlapic->lvt_last[idx], val);
} }
}
static void static void
vlapic_mask_lvts(struct acrn_vlapic *vlapic) vlapic_mask_lvts(struct acrn_vlapic *vlapic)
@ -754,9 +767,7 @@ vlapic_fire_lvt(struct acrn_vlapic *vlapic, uint32_t lvt)
uint32_t vec, mode; uint32_t vec, mode;
struct acrn_vcpu *vcpu = vlapic->vcpu; struct acrn_vcpu *vcpu = vlapic->vcpu;
if ((lvt & APIC_LVT_M) != 0U) { if ((lvt & APIC_LVT_M) == 0U) {
return;
}
vec = lvt & APIC_LVT_VECTOR; vec = lvt & APIC_LVT_VECTOR;
mode = lvt & APIC_LVT_DM; mode = lvt & APIC_LVT_DM;
@ -776,7 +787,8 @@ vlapic_fire_lvt(struct acrn_vlapic *vlapic, uint32_t lvt)
default: default:
/* Other modes ignored */ /* Other modes ignored */
pr_warn("func:%s other mode is not support\n",__func__); pr_warn("func:%s other mode is not support\n",__func__);
return; break;
}
} }
return; return;
} }
@ -903,7 +915,7 @@ vlapic_process_eoi(struct acrn_vlapic *vlapic)
/* hook to vIOAPIC */ /* hook to vIOAPIC */
vioapic_process_eoi(vlapic->vm, vector); vioapic_process_eoi(vlapic->vm, vector);
} }
return; break;
} }
} }
@ -932,6 +944,7 @@ static int32_t
vlapic_trigger_lvt(struct acrn_vlapic *vlapic, uint32_t vector) vlapic_trigger_lvt(struct acrn_vlapic *vlapic, uint32_t vector)
{ {
uint32_t lvt; uint32_t lvt;
int32_t ret = 0;
struct acrn_vcpu *vcpu = vlapic->vcpu; struct acrn_vcpu *vcpu = vlapic->vcpu;
if (vlapic_enabled(vlapic) == false) { if (vlapic_enabled(vlapic) == false) {
@ -955,8 +968,7 @@ vlapic_trigger_lvt(struct acrn_vlapic *vlapic, uint32_t vector)
*/ */
break; break;
} }
return 0; } else {
}
switch (vector) { switch (vector) {
case APIC_LVT_LINT0: case APIC_LVT_LINT0:
@ -983,14 +995,20 @@ vlapic_trigger_lvt(struct acrn_vlapic *vlapic, uint32_t vector)
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_CMCI_LVT); lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_CMCI_LVT);
break; break;
default: default:
return -EINVAL; lvt = 0U; /* make MISRA happy */
ret = -EINVAL;
break;
} }
if (ret == 0) {
if (vector < 16U) { if (vector < 16U) {
vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR); vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR);
} else { } else {
vlapic_fire_lvt(vlapic, lvt); vlapic_fire_lvt(vlapic, lvt);
} }
return 0; }
}
return ret;
} }
/* /*
@ -1167,9 +1185,7 @@ vlapic_process_init_sipi(struct acrn_vcpu* target_vcpu, uint32_t mode,
uint32_t icr_low, uint16_t vcpu_id) uint32_t icr_low, uint16_t vcpu_id)
{ {
if (mode == APIC_DELMODE_INIT) { if (mode == APIC_DELMODE_INIT) {
if ((icr_low & APIC_LEVEL_MASK) == APIC_LEVEL_DEASSERT) { if ((icr_low & APIC_LEVEL_MASK) != APIC_LEVEL_DEASSERT) {
return;
}
dev_dbg(ACRN_DBG_LAPIC, dev_dbg(ACRN_DBG_LAPIC,
"Sending INIT from VCPU %hu to %hu", "Sending INIT from VCPU %hu to %hu",
@ -1183,12 +1199,11 @@ vlapic_process_init_sipi(struct acrn_vcpu* target_vcpu, uint32_t mode,
* wait-for-SIPI state. * wait-for-SIPI state.
*/ */
target_vcpu->arch.nr_sipi = 1U; target_vcpu->arch.nr_sipi = 1U;
}
} else if (mode == APIC_DELMODE_STARTUP) { } else if (mode == APIC_DELMODE_STARTUP) {
/* Ignore SIPIs in any state other than wait-for-SIPI */ /* Ignore SIPIs in any state other than wait-for-SIPI */
if ((target_vcpu->state != VCPU_INIT) || if ((target_vcpu->state == VCPU_INIT) &&
(target_vcpu->arch.nr_sipi == 0U)) { (target_vcpu->arch.nr_sipi != 0U)) {
return;
}
dev_dbg(ACRN_DBG_LAPIC, dev_dbg(ACRN_DBG_LAPIC,
"Sending SIPI from VCPU %hu to %hu with vector %u", "Sending SIPI from VCPU %hu to %hu with vector %u",
@ -1196,9 +1211,7 @@ vlapic_process_init_sipi(struct acrn_vcpu* target_vcpu, uint32_t mode,
(icr_low & APIC_VECTOR_MASK)); (icr_low & APIC_VECTOR_MASK));
target_vcpu->arch.nr_sipi--; target_vcpu->arch.nr_sipi--;
if (target_vcpu->arch.nr_sipi > 0U) { if (target_vcpu->arch.nr_sipi <= 0U) {
return;
}
pr_err("Start Secondary VCPU%hu for VM[%d]...", pr_err("Start Secondary VCPU%hu for VM[%d]...",
target_vcpu->vcpu_id, target_vcpu->vcpu_id,
@ -1207,6 +1220,9 @@ vlapic_process_init_sipi(struct acrn_vcpu* target_vcpu, uint32_t mode,
schedule_vcpu(target_vcpu); schedule_vcpu(target_vcpu);
} }
} }
}
return;
}
static int32_t static int32_t
vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic) vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
@ -1320,10 +1336,11 @@ vlapic_pending_intr(const struct acrn_vlapic *vlapic, uint32_t *vecptr)
const struct lapic_regs *lapic = &(vlapic->apic_page); const struct lapic_regs *lapic = &(vlapic->apic_page);
uint32_t i, vector, val, bitpos; uint32_t i, vector, val, bitpos;
const struct lapic_reg *irrptr; const struct lapic_reg *irrptr;
int32_t ret = 0;
if (is_apicv_intr_delivery_supported()) { if (is_apicv_intr_delivery_supported()) {
return apicv_pending_intr(vlapic); ret = apicv_pending_intr(vlapic);
} } else {
irrptr = &lapic->irr[0]; irrptr = &lapic->irr[0];
@ -1338,12 +1355,13 @@ vlapic_pending_intr(const struct acrn_vlapic *vlapic, uint32_t *vecptr)
if (vecptr != NULL) { if (vecptr != NULL) {
*vecptr = vector; *vecptr = vector;
} }
return 1; ret = 1;
} }
break; break;
} }
} }
return 0; }
return ret;
} }
/** /**