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hv:merge struct lapic and lapic_regs to lapic_regs

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merge these two structures to lapic_regs

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Mingqiang Chi
2018-06-29 14:09:44 +08:00
committed by lijinxia
parent 7a66c317b5
commit eaa5418fba
5 changed files with 80 additions and 90 deletions
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72
hypervisor/arch/x86/lapic.c
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@@ -248,22 +248,26 @@ void save_lapic(struct lapic_regs *regs)
regs->ppr = read_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER);
regs->ldr = read_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER);
regs->dfr = read_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER);
regs->tmr[0] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0);
regs->tmr[1] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1);
regs->tmr[2] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2);
regs->tmr[3] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3);
regs->tmr[4] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4);
regs->tmr[5] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5);
regs->tmr[6] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6);
regs->tmr[7] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7);
regs->tmr[0].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0);
regs->tmr[1].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1);
regs->tmr[2].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2);
regs->tmr[3].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3);
regs->tmr[4].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4);
regs->tmr[5].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5);
regs->tmr[6].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6);
regs->tmr[7].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7);
regs->svr = read_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER);
regs->lvtt = read_lapic_reg32(LAPIC_LVT_TIMER_REGISTER);
regs->lvt0 = read_lapic_reg32(LAPIC_LVT_LINT0_REGISTER);
regs->lvt1 = read_lapic_reg32(LAPIC_LVT_LINT1_REGISTER);
regs->lvterr = read_lapic_reg32(LAPIC_LVT_ERROR_REGISTER);
regs->ticr = read_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER);
regs->tccr = read_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER);
regs->tdcr = read_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER);
regs->lvt[APIC_LVT_TIMER].val =
read_lapic_reg32(LAPIC_LVT_TIMER_REGISTER);
regs->lvt[APIC_LVT_LINT0].val =
read_lapic_reg32(LAPIC_LVT_LINT0_REGISTER);
regs->lvt[APIC_LVT_LINT1].val =
read_lapic_reg32(LAPIC_LVT_LINT1_REGISTER);
regs->lvt[APIC_LVT_ERROR].val =
read_lapic_reg32(LAPIC_LVT_ERROR_REGISTER);
regs->icr_timer = read_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER);
regs->ccr_timer = read_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER);
regs->dcr_timer = read_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER);
}
static void restore_lapic(struct lapic_regs *regs)
@@ -273,27 +277,31 @@ static void restore_lapic(struct lapic_regs *regs)
write_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER, regs->ldr );
write_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER, regs->dfr );
write_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER, regs->svr );
write_lapic_reg32(LAPIC_LVT_TIMER_REGISTER, regs->lvtt );
write_lapic_reg32(LAPIC_LVT_TIMER_REGISTER,
regs->lvt[APIC_LVT_TIMER].val);
write_lapic_reg32(LAPIC_LVT_LINT0_REGISTER, regs->lvt0 );
write_lapic_reg32(LAPIC_LVT_LINT1_REGISTER, regs->lvt1 );
write_lapic_reg32(LAPIC_LVT_LINT0_REGISTER,
regs->lvt[APIC_LVT_LINT0].val);
write_lapic_reg32(LAPIC_LVT_LINT1_REGISTER,
regs->lvt[APIC_LVT_LINT1].val);
write_lapic_reg32(LAPIC_LVT_ERROR_REGISTER, regs->lvterr );
write_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER, regs->ticr );
write_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER, regs->tdcr );
write_lapic_reg32(LAPIC_LVT_ERROR_REGISTER,
regs->lvt[APIC_LVT_ERROR].val);
write_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER, regs->icr_timer);
write_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER, regs->dcr_timer);
write_lapic_reg32(LAPIC_ARBITRATION_PRIORITY_REGISTER, regs->apr );
write_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER, regs->ppr );
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0, regs->tmr[0] );
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1, regs->tmr[1] );
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2, regs->tmr[2] );
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3, regs->tmr[3] );
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4, regs->tmr[4] );
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5, regs->tmr[5] );
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6, regs->tmr[6] );
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7, regs->tmr[7] );
write_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER, regs->tccr );
write_lapic_reg32(LAPIC_ARBITRATION_PRIORITY_REGISTER, regs->apr);
write_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER, regs->ppr);
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0, regs->tmr[0].val);
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1, regs->tmr[1].val);
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2, regs->tmr[2].val);
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3, regs->tmr[3].val);
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4, regs->tmr[4].val);
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5, regs->tmr[5].val);
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6, regs->tmr[6].val);
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7, regs->tmr[7].val);
write_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER, regs->ccr_timer);
}
void suspend_lapic(void)