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hv:Fix Implict conversion:actual to formal param

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MISRAC has requirement about implict conversion: actual to formal
param. This patch is used to fix part of these violations.

1.Add a new structure seg_desc_vmcs to hold the VMCS field address of
segment selector to clean up seg_desc structure.

2.Add the definition of maximum MSI entry and the relevant judgement.

3.The violations in shell.c, logmsg.c will be fixed in other series of
patches with modification of function snprintf(), vsnprintf() and other
related usages.

v1->v2:
  *Move the definition of struct seg_desc_vmcs from instr_emul.h to
   instr_emul.c.
  *Modify the formal parameter type in function definition from uint8_t
   to char instead of using cast.
  *Drop the const declaration for char data in formal parameter.

v2->v3:
  *update the data missing conversion.
  *change type of internal parameter len to avoid casting in npklog.c.
  *change the conversion from signed char to unsigned int in
   uart16550_getc() to solve sign-extension.

Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Junjun Shan
2018-09-17 13:39:40 +08:00
committed by lijinxia
parent 8f0cb5630d
commit eb8c4fb0d5
12 changed files with 80 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

81
hypervisor/arch/x86/guest/instr_emul.c
View File

@@ -182,58 +182,69 @@ static uint64_t size2mask[9] = {
#define VMX_INVALID_VMCS_FIELD 0xffffffffU
static void encode_vmcs_seg_desc(enum cpu_reg_name seg, struct seg_desc *desc)
/*
* This struct seg_desc_vmcs is defined separately to hold the vmcs field
* address of segment selector.
*/
struct seg_desc_vmcs {
uint32_t base_field;
uint32_t limit_field;
uint32_t access_field;
};
static void encode_vmcs_seg_desc(enum cpu_reg_name seg,
struct seg_desc_vmcs *desc)
{
switch (seg) {
case CPU_REG_ES:
desc->base = VMX_GUEST_ES_BASE;
desc->limit = VMX_GUEST_ES_LIMIT;
desc->access = VMX_GUEST_ES_ATTR;
desc->base_field = VMX_GUEST_ES_BASE;
desc->limit_field = VMX_GUEST_ES_LIMIT;
desc->access_field = VMX_GUEST_ES_ATTR;
break;
case CPU_REG_CS:
desc->base = VMX_GUEST_CS_BASE;
desc->limit = VMX_GUEST_CS_LIMIT;
desc->access = VMX_GUEST_CS_ATTR;
desc->base_field = VMX_GUEST_CS_BASE;
desc->limit_field = VMX_GUEST_CS_LIMIT;
desc->access_field = VMX_GUEST_CS_ATTR;
break;
case CPU_REG_SS:
desc->base = VMX_GUEST_SS_BASE;
desc->limit = VMX_GUEST_SS_LIMIT;
desc->access = VMX_GUEST_SS_ATTR;
desc->base_field = VMX_GUEST_SS_BASE;
desc->limit_field = VMX_GUEST_SS_LIMIT;
desc->access_field = VMX_GUEST_SS_ATTR;
break;
case CPU_REG_DS:
desc->base = VMX_GUEST_DS_BASE;
desc->limit = VMX_GUEST_DS_LIMIT;
desc->access = VMX_GUEST_DS_ATTR;
desc->base_field = VMX_GUEST_DS_BASE;
desc->limit_field = VMX_GUEST_DS_LIMIT;
desc->access_field = VMX_GUEST_DS_ATTR;
break;
case CPU_REG_FS:
desc->base = VMX_GUEST_FS_BASE;
desc->limit = VMX_GUEST_FS_LIMIT;
desc->access = VMX_GUEST_FS_ATTR;
desc->base_field = VMX_GUEST_FS_BASE;
desc->limit_field = VMX_GUEST_FS_LIMIT;
desc->access_field = VMX_GUEST_FS_ATTR;
break;
case CPU_REG_GS:
desc->base = VMX_GUEST_GS_BASE;
desc->limit = VMX_GUEST_GS_LIMIT;
desc->access = VMX_GUEST_GS_ATTR;
desc->base_field = VMX_GUEST_GS_BASE;
desc->limit_field = VMX_GUEST_GS_LIMIT;
desc->access_field = VMX_GUEST_GS_ATTR;
break;
case CPU_REG_TR:
desc->base = VMX_GUEST_TR_BASE;
desc->limit = VMX_GUEST_TR_LIMIT;
desc->access = VMX_GUEST_TR_ATTR;
desc->base_field = VMX_GUEST_TR_BASE;
desc->limit_field = VMX_GUEST_TR_LIMIT;
desc->access_field = VMX_GUEST_TR_ATTR;
break;
case CPU_REG_LDTR:
desc->base = VMX_GUEST_LDTR_BASE;
desc->limit = VMX_GUEST_LDTR_LIMIT;
desc->access = VMX_GUEST_LDTR_ATTR;
desc->base_field = VMX_GUEST_LDTR_BASE;
desc->limit_field = VMX_GUEST_LDTR_LIMIT;
desc->access_field = VMX_GUEST_LDTR_ATTR;
break;
case CPU_REG_IDTR:
desc->base = VMX_GUEST_IDTR_BASE;
desc->limit = VMX_GUEST_IDTR_LIMIT;
desc->access = 0xffffffffU;
desc->base_field = VMX_GUEST_IDTR_BASE;
desc->limit_field = VMX_GUEST_IDTR_LIMIT;
desc->access_field = 0xffffffffU;
break;
case CPU_REG_GDTR:
desc->base = VMX_GUEST_GDTR_BASE;
desc->limit = VMX_GUEST_GDTR_LIMIT;
desc->access = 0xffffffffU;
desc->base_field = VMX_GUEST_GDTR_BASE;
desc->limit_field = VMX_GUEST_GDTR_LIMIT;
desc->access_field = 0xffffffffU;
break;
default:
pr_err("%s: invalid seg %d", __func__, seg);
@@ -363,14 +374,14 @@ static void vm_set_register(struct vcpu *vcpu, enum cpu_reg_name reg,
*/
static void vm_get_seg_desc(enum cpu_reg_name seg, struct seg_desc *desc)
{
struct seg_desc tdesc = {0UL, 0U, 0U};
struct seg_desc_vmcs tdesc = {0U, 0U, 0U};
/* tdesc->access != 0xffffffffU in this function */
encode_vmcs_seg_desc(seg, &tdesc);
desc->base = exec_vmread(tdesc.base);
desc->limit = exec_vmread32(tdesc.limit);
desc->access = exec_vmread32(tdesc.access);
desc->base = exec_vmread(tdesc.base_field);
desc->limit = exec_vmread32(tdesc.limit_field);
desc->access = exec_vmread32(tdesc.access_field);
}
static void get_guest_paging_info(struct vcpu *vcpu, struct instr_emul_ctxt *emul_ctxt,

1
hypervisor/arch/x86/guest/instr_emul.h
View File

@@ -154,7 +154,6 @@ struct seg_desc {
uint32_t access;
};
/*
* Protections are chosen from these bits, or-ed together
*/

14
hypervisor/arch/x86/irq.c
View File

@@ -45,7 +45,8 @@ uint32_t alloc_irq_num(uint32_t req_irq)
}
if (irq != IRQ_INVALID) {
bitmap_set_nolock(irq & 0x3FU, irq_alloc_bitmap + (irq >> 6U));
bitmap_set_nolock((uint16_t)(irq & 0x3FU),
irq_alloc_bitmap + (irq >> 6U));
}
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
return irq;
@@ -67,7 +68,7 @@ void free_irq_num(uint32_t irq)
if ((irq_is_gsi(irq) == false)
&& (desc->vector <= VECTOR_DYNAMIC_END)) {
spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
bitmap_test_and_clear_nolock(irq & 0x3FU,
bitmap_test_and_clear_nolock((uint16_t)(irq & 0x3FU),
irq_alloc_bitmap + (irq >> 6U));
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
}
@@ -333,7 +334,8 @@ void dispatch_interrupt(struct intr_excp_ctx *ctx)
goto ERR;
}
if (bitmap_test(irq & 0x3FU, irq_alloc_bitmap + (irq >> 6U)) == 0U) {
if (bitmap_test((uint16_t)(irq & 0x3FU),
irq_alloc_bitmap + (irq >> 6U)) == 0U) {
/* mask irq if possible */
goto ERR;
}
@@ -403,7 +405,8 @@ void get_cpu_interrupt_info(char *str_arg, int str_max)
for (irq = 0U; irq < NR_IRQS; irq++) {
vector = irq_to_vector(irq);
if (bitmap_test(irq & 0x3FU, irq_alloc_bitmap + (irq >> 6U))
if (bitmap_test((uint16_t)(irq & 0x3FU),
irq_alloc_bitmap + (irq >> 6U))
&& (vector != VECTOR_INVALID)) {
len = snprintf(str, size, "\r\n%d\t0x%X", irq, vector);
size -= len;
@@ -441,7 +444,8 @@ static void init_irq_descs(void)
irq_desc_array[irq].vector = vr;
vector_to_irq[vr] = irq;
bitmap_set_nolock(irq & 0x3FU, irq_alloc_bitmap + (irq >> 6U));
bitmap_set_nolock((uint16_t)(irq & 0x3FU),
irq_alloc_bitmap + (irq >> 6U));
}
}

2
hypervisor/arch/x86/notify.c
View File

@@ -50,7 +50,7 @@ void smp_call_function(uint64_t mask, smp_call_func_t func, void *data)
}
pcpu_id = ffs64(mask);
}
send_dest_ipi(smp_call_mask, VECTOR_NOTIFY_VCPU,
send_dest_ipi((uint32_t)smp_call_mask, VECTOR_NOTIFY_VCPU,
INTR_LAPIC_ICR_LOGICAL);
/* wait for current smp call complete */
wait_sync_change(&smp_call_mask, 0UL);