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hv: some coding style fixes

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Fix issues reported by checkpatch.pl

Tracked-On: #5917
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
dongshen 2021-05-06 14:14:39 -07:00 committed by wenlingz
parent f7ef46f0d9
commit ebadf00de8
7 changed files with 20 additions and 25 deletions
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3
hypervisor/arch/x86/guest/vcpuid.c
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@ -61,8 +61,7 @@ static inline const struct vcpuid_entry *find_vcpuid_entry(const struct acrn_vcp
if ((leaf & 0x80000000U) != 0U) { if ((leaf & 0x80000000U) != 0U) {
limit = vm->vcpuid_xlevel; limit = vm->vcpuid_xlevel;
} } else {
else {
limit = vm->vcpuid_level; limit = vm->vcpuid_level;
} }

3
hypervisor/arch/x86/rdt.c
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@ -216,9 +216,8 @@ bool is_platform_rdt_capable(void)
return ret; return ret;
} }
#else #else
uint64_t clos2pqr_msr(uint16_t clos) uint64_t clos2pqr_msr(__unused uint16_t clos)
{ {
(void)(clos);
return 0UL; return 0UL;
} }

11
hypervisor/arch/x86/timer.c
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@ -19,7 +19,7 @@
#define CAL_MS 10U #define CAL_MS 10U
#define MIN_TIMER_PERIOD_US 500U #define MIN_TIMER_PERIOD_US 500U
static uint32_t tsc_khz = 0U; static uint32_t tsc_khz;
uint64_t rdtsc(void) uint64_t rdtsc(void)
{ {
@ -74,8 +74,7 @@ static bool local_add_timer(struct per_cpu_timers *cpu_timer,
tmp = container_of(pos, struct hv_timer, node); tmp = container_of(pos, struct hv_timer, node);
if (tmp->fire_tsc < tsc) { if (tmp->fire_tsc < tsc) {
prev = &tmp->node; prev = &tmp->node;
} } else {
else {
break; break;
} }
} }
@ -155,7 +154,7 @@ static void timer_softirq(uint16_t pcpu_id)
{ {
struct per_cpu_timers *cpu_timer; struct per_cpu_timers *cpu_timer;
struct hv_timer *timer; struct hv_timer *timer;
struct list_head *pos, *n; const struct list_head *pos, *n;
uint32_t tries = MAX_TIMER_ACTIONS; uint32_t tries = MAX_TIMER_ACTIONS;
uint64_t current_tsc = rdtsc(); uint64_t current_tsc = rdtsc();
@ -268,7 +267,7 @@ static uint64_t pit_calibrate_tsc(uint32_t cal_ms_arg)
static uint64_t native_calibrate_tsc(void) static uint64_t native_calibrate_tsc(void)
{ {
uint64_t tsc_hz = 0UL; uint64_t tsc_hz = 0UL;
struct cpuinfo_x86 *cpu_info = get_pcpu_info(); const struct cpuinfo_x86 *cpu_info = get_pcpu_info();
if (cpu_info->cpuid_level >= 0x15U) { if (cpu_info->cpuid_level >= 0x15U) {
uint32_t eax_denominator, ebx_numerator, ecx_hz, reserved; uint32_t eax_denominator, ebx_numerator, ecx_hz, reserved;
@ -284,6 +283,7 @@ static uint64_t native_calibrate_tsc(void)
if ((tsc_hz == 0UL) && (cpu_info->cpuid_level >= 0x16U)) { if ((tsc_hz == 0UL) && (cpu_info->cpuid_level >= 0x16U)) {
uint32_t eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; uint32_t eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
cpuid_subleaf(0x16U, 0x0U, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); cpuid_subleaf(0x16U, 0x0U, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
tsc_hz = (uint64_t) eax_base_mhz * 1000000U; tsc_hz = (uint64_t) eax_base_mhz * 1000000U;
} }
@ -294,6 +294,7 @@ static uint64_t native_calibrate_tsc(void)
void calibrate_tsc(void) void calibrate_tsc(void)
{ {
uint64_t tsc_hz; uint64_t tsc_hz;
tsc_hz = native_calibrate_tsc(); tsc_hz = native_calibrate_tsc();
if (tsc_hz == 0U) { if (tsc_hz == 0U) {
tsc_hz = pit_calibrate_tsc(CAL_MS); tsc_hz = pit_calibrate_tsc(CAL_MS);

4
hypervisor/debug/profiling.c
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@ -683,8 +683,7 @@ static void profiling_pmi_handler(uint32_t irq, __unused void *data)
if (msrop->msr_id != MSR_IA32_PERF_GLOBAL_CTRL) { if (msrop->msr_id != MSR_IA32_PERF_GLOBAL_CTRL) {
msr_write(msrop->msr_id, msrop->value); msr_write(msrop->msr_id, msrop->value);
} }
} } else {
else {
if (((perf_ovf_status >> msrop->param) & 0x1U) > 0U) { if (((perf_ovf_status >> msrop->param) & 0x1U) > 0U) {
msr_write(msrop->msr_id, msrop->value); msr_write(msrop->msr_id, msrop->value);
} }
@ -1391,6 +1390,7 @@ void profiling_setup(void)
{ {
uint16_t cpu; uint16_t cpu;
int32_t retval; int32_t retval;
dev_dbg(DBG_LEVEL_PROFILING, "%s: entering", __func__); dev_dbg(DBG_LEVEL_PROFILING, "%s: entering", __func__);
cpu = get_pcpu_id(); cpu = get_pcpu_id();
/* support PMI notification, SOS_VM will register all CPU */ /* support PMI notification, SOS_VM will register all CPU */

5
hypervisor/debug/shell.c
View File

@ -1368,11 +1368,8 @@ static int32_t shell_cpuid(int32_t argc, char **argv)
return 0; return 0;
} }
static int32_t shell_reboot(int32_t argc, char **argv) static int32_t shell_reboot(__unused int32_t argc, __unused char **argv)
{ {
(void)argc;
(void)argv;
reset_host(); reset_host();
return 0; return 0;
} }

3
hypervisor/dm/vpci/vhostbridge.c
View File

@ -117,8 +117,7 @@ static void init_vhostbridge(struct pci_vdev *vdev)
* and UOS_VIRT_PCI_MMCFG_BASE(0xE0000000) is fine. The trailing 1 is a ECAM enable-bit * and UOS_VIRT_PCI_MMCFG_BASE(0xE0000000) is fine. The trailing 1 is a ECAM enable-bit
*/ */
pciexbar_low = UOS_VIRT_PCI_MMCFG_BASE | 0x1U; pciexbar_low = UOS_VIRT_PCI_MMCFG_BASE | 0x1U;
} } else {
else {
/*Inject physical ECAM value to SOS vhostbridge since SOS may check PCIe-MMIO Base Address with it */ /*Inject physical ECAM value to SOS vhostbridge since SOS may check PCIe-MMIO Base Address with it */
phys_did = pci_pdev_read_cfg(hostbridge_bdf, PCIR_DEVICE, 2); phys_did = pci_pdev_read_cfg(hostbridge_bdf, PCIR_DEVICE, 2);
for (i = 0U; i < (sizeof(hostbridge_did_highbytes) / sizeof(uint32_t)); i++) { for (i = 0U; i < (sizeof(hostbridge_did_highbytes) / sizeof(uint32_t)); i++) {