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HV: instr_emul: make integer conversion explicit
This patch makes necessary integer narrowing and/or signedness conversion explicit. While some narrowing are expected behavior, the correctness of the others relies on the specifications of some interfaces (e.g. the higher 32-bit of what exec_vmread() returns is all 0s if the given field is 32-bit). Add a stub for now to avoid missing them. Signed-off-by: Junjie Mao <junjie.mao@intel.com>
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@ -291,9 +291,9 @@ vie_read_bytereg(struct vcpu *vcpu, struct vie *vie, uint8_t *rval)
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* base register right by 8 bits (%ah = %rax >> 8).
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*/
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if (lhbr != 0)
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*rval = val >> 8;
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*rval = (uint8_t)(val >> 8);
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else
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*rval = val;
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*rval = (uint8_t)val;
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return error;
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}
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@ -440,7 +440,7 @@ emulate_mov(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
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size = 1U; /* override for byte operation */
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error = memread(vcpu, gpa, &val, size, arg);
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if (error == 0)
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error = vie_write_bytereg(vcpu, vie, val);
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error = vie_write_bytereg(vcpu, vie, (uint8_t)val);
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break;
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case 0x8BU:
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/*
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@ -503,7 +503,7 @@ emulate_mov(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
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* REX.W + C7/0 mov r/m64, imm32
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* (sign-extended to 64-bits)
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*/
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val = vie->immediate & size2mask[size];
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val = (uint64_t)vie->immediate & size2mask[size];
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error = memwrite(vcpu, gpa, val, size, arg);
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break;
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default:
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@ -1020,7 +1020,7 @@ emulate_or(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
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* perform the operation with the pre-fetched immediate
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* operand and write the result
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*/
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result = val1 | vie->immediate;
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result = val1 | (uint64_t)vie->immediate;
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error = memwrite(vcpu, gpa, result, size, arg);
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break;
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case 0x09U:
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@ -1414,8 +1414,8 @@ emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
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mem_region_read_t memread, __unused mem_region_write_t memwrite,
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void *memarg)
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{
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uint64_t val, rflags;
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int error, bitmask;
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uint64_t val, rflags, bitmask;
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int error;
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uint32_t bitoff;
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/*
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@ -1438,8 +1438,8 @@ emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
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* Intel SDM, Vol 2, Table 3-2:
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* "Range of Bit Positions Specified by Bit Offset Operands"
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*/
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bitmask = vie->opsize * 8 - 1;
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bitoff = vie->immediate & bitmask;
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bitmask = (uint64_t)vie->opsize * 8UL - 1UL;
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bitoff = (uint64_t)vie->immediate & bitmask;
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/* Copy the bit into the Carry flag in %rflags */
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if ((val & (1UL << bitoff)) != 0U)
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@ -1708,7 +1708,7 @@ vie_init(struct vie *vie, struct vcpu *vcpu)
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return ret;
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} else if (ret < 0)
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return ret;
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vie->num_valid = inst_len;
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vie->num_valid = (uint8_t)inst_len;
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}
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return 0;
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@ -2132,7 +2132,7 @@ decode_moffset(struct vie *vie)
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u.buf[i] = x;
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vie_advance(vie);
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}
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vie->displacement = u.u64;
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vie->displacement = (int64_t)u.u64;
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return 0;
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}
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@ -114,8 +114,8 @@ int vm_get_seg_desc(struct vcpu *vcpu, enum cpu_reg_name seg,
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return -EINVAL;
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desc->base = exec_vmread(base);
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desc->limit = exec_vmread(limit);
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desc->access = exec_vmread(access);
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desc->limit = (uint32_t)exec_vmread(limit);
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desc->access = (uint32_t)exec_vmread(access);
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return 0;
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}
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@ -313,7 +313,7 @@ int decode_instruction(struct vcpu *vcpu)
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return retval;
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}
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csar = exec_vmread(VMX_GUEST_CS_ATTR);
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csar = (uint32_t)exec_vmread(VMX_GUEST_CS_ATTR);
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get_guest_paging_info(vcpu, emul_cnx, csar);
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cpu_mode = get_vcpu_mode(vcpu);
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@ -402,7 +402,18 @@
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/* External Interfaces */
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int exec_vmxon_instr(uint16_t pcpu_id);
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/**
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* Read field from VMCS.
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*
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* Refer to Chapter 24, Vol. 3 in SDM for the width of VMCS fields.
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*
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* @return full contents in IA-32e mode for 64-bit fields.
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* @return the lower 32-bit outside IA-32e mode for 64-bit fields.
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* @return full contents for 32-bit fields, with higher 32-bit set to 0.
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*/
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uint64_t exec_vmread(uint32_t field);
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uint64_t exec_vmread64(uint32_t field_full);
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void exec_vmwrite(uint32_t field, uint64_t value);
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void exec_vmwrite64(uint32_t field_full, uint64_t value);
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