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hv: add suffix(U) in vmx.h to come up MISRA-C
MISRA-C required the suffix(U), such as: (1U << 0) ---> (1U << 0U) This patch will add the suffix(U) to come up MISRA-C. Tracked-On: #1385 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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Wei Liu
wenlingz
parent
8787b65fde
commit
eebccac2a7
@ -262,112 +262,112 @@
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#define VMX_EXIT_REASON_XRSTORS 0x00000040U
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/* VMX execution control bits (pin based) */
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#define VMX_PINBASED_CTLS_IRQ_EXIT (1U<<0)
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#define VMX_PINBASED_CTLS_NMI_EXIT (1U<<3)
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#define VMX_PINBASED_CTLS_VIRT_NMI (1U<<5)
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#define VMX_PINBASED_CTLS_ENABLE_PTMR (1U<<6)
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#define VMX_PINBASED_CTLS_POST_IRQ (1U<<7)
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#define VMX_PINBASED_CTLS_IRQ_EXIT (1U<<0U)
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#define VMX_PINBASED_CTLS_NMI_EXIT (1U<<3U)
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#define VMX_PINBASED_CTLS_VIRT_NMI (1U<<5U)
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#define VMX_PINBASED_CTLS_ENABLE_PTMR (1U<<6U)
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#define VMX_PINBASED_CTLS_POST_IRQ (1U<<7U)
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/* VMX execution control bits (processor based) */
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#define VMX_PROCBASED_CTLS_IRQ_WIN (1U<<2)
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#define VMX_PROCBASED_CTLS_TSC_OFF (1U<<3)
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#define VMX_PROCBASED_CTLS_HLT (1U<<7)
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#define VMX_PROCBASED_CTLS_INVLPG (1U<<9)
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#define VMX_PROCBASED_CTLS_MWAIT (1U<<10)
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#define VMX_PROCBASED_CTLS_RDPMC (1U<<11)
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#define VMX_PROCBASED_CTLS_RDTSC (1U<<12)
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#define VMX_PROCBASED_CTLS_CR3_LOAD (1U<<15)
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#define VMX_PROCBASED_CTLS_CR3_STORE (1U<<16)
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#define VMX_PROCBASED_CTLS_CR8_LOAD (1U<<19)
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#define VMX_PROCBASED_CTLS_CR8_STORE (1U<<20)
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#define VMX_PROCBASED_CTLS_TPR_SHADOW (1U<<21)
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#define VMX_PROCBASED_CTLS_NMI_WINEXIT (1U<<22)
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#define VMX_PROCBASED_CTLS_MOV_DR (1U<<23)
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#define VMX_PROCBASED_CTLS_UNCOND_IO (1U<<24)
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#define VMX_PROCBASED_CTLS_IO_BITMAP (1U<<25)
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#define VMX_PROCBASED_CTLS_MON_TRAP (1U<<27)
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#define VMX_PROCBASED_CTLS_MSR_BITMAP (1U<<28)
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#define VMX_PROCBASED_CTLS_MONITOR (1U<<29)
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#define VMX_PROCBASED_CTLS_PAUSE (1U<<30)
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#define VMX_PROCBASED_CTLS_SECONDARY (1U<<31)
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#define VMX_PROCBASED_CTLS2_VAPIC (1U<<0)
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#define VMX_PROCBASED_CTLS2_EPT (1U<<1)
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#define VMX_PROCBASED_CTLS2_DESC_TABLE (1U<<2)
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#define VMX_PROCBASED_CTLS2_RDTSCP (1U<<3)
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#define VMX_PROCBASED_CTLS2_VX2APIC (1U<<4)
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#define VMX_PROCBASED_CTLS2_VPID (1U<<5)
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#define VMX_PROCBASED_CTLS2_WBINVD (1U<<6)
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#define VMX_PROCBASED_CTLS2_UNRESTRICT (1U<<7)
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#define VMX_PROCBASED_CTLS2_VAPIC_REGS (1U<<8)
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#define VMX_PROCBASED_CTLS2_VIRQ (1U<<9)
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#define VMX_PROCBASED_CTLS2_PAUSE_LOOP (1U<<10)
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#define VMX_PROCBASED_CTLS2_RDRAND (1U<<11)
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#define VMX_PROCBASED_CTLS2_INVPCID (1U<<12)
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#define VMX_PROCBASED_CTLS2_VM_FUNCS (1U<<13)
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#define VMX_PROCBASED_CTLS2_VMCS_SHADW (1U<<14)
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#define VMX_PROCBASED_CTLS2_RDSEED (1U<<16)
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#define VMX_PROCBASED_CTLS2_EPT_VE (1U<<18)
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#define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1U<<20)
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#define VMX_PROCBASED_CTLS_IRQ_WIN (1U<<2U)
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#define VMX_PROCBASED_CTLS_TSC_OFF (1U<<3U)
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#define VMX_PROCBASED_CTLS_HLT (1U<<7U)
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#define VMX_PROCBASED_CTLS_INVLPG (1U<<9U)
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#define VMX_PROCBASED_CTLS_MWAIT (1U<<10U)
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#define VMX_PROCBASED_CTLS_RDPMC (1U<<11U)
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#define VMX_PROCBASED_CTLS_RDTSC (1U<<12U)
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#define VMX_PROCBASED_CTLS_CR3_LOAD (1U<<15U)
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#define VMX_PROCBASED_CTLS_CR3_STORE (1U<<16U)
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#define VMX_PROCBASED_CTLS_CR8_LOAD (1U<<19U)
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#define VMX_PROCBASED_CTLS_CR8_STORE (1U<<20U)
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#define VMX_PROCBASED_CTLS_TPR_SHADOW (1U<<21U)
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#define VMX_PROCBASED_CTLS_NMI_WINEXIT (1U<<22U)
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#define VMX_PROCBASED_CTLS_MOV_DR (1U<<23U)
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#define VMX_PROCBASED_CTLS_UNCOND_IO (1U<<24U)
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#define VMX_PROCBASED_CTLS_IO_BITMAP (1U<<25U)
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#define VMX_PROCBASED_CTLS_MON_TRAP (1U<<27U)
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#define VMX_PROCBASED_CTLS_MSR_BITMAP (1U<<28U)
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#define VMX_PROCBASED_CTLS_MONITOR (1U<<29U)
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#define VMX_PROCBASED_CTLS_PAUSE (1U<<30U)
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#define VMX_PROCBASED_CTLS_SECONDARY (1U<<31U)
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#define VMX_PROCBASED_CTLS2_VAPIC (1U<<0U)
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#define VMX_PROCBASED_CTLS2_EPT (1U<<1U)
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#define VMX_PROCBASED_CTLS2_DESC_TABLE (1U<<2U)
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#define VMX_PROCBASED_CTLS2_RDTSCP (1U<<3U)
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#define VMX_PROCBASED_CTLS2_VX2APIC (1U<<4U)
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#define VMX_PROCBASED_CTLS2_VPID (1U<<5U)
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#define VMX_PROCBASED_CTLS2_WBINVD (1U<<6U)
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#define VMX_PROCBASED_CTLS2_UNRESTRICT (1U<<7U)
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#define VMX_PROCBASED_CTLS2_VAPIC_REGS (1U<<8U)
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#define VMX_PROCBASED_CTLS2_VIRQ (1U<<9U)
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#define VMX_PROCBASED_CTLS2_PAUSE_LOOP (1U<<10U)
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#define VMX_PROCBASED_CTLS2_RDRAND (1U<<11U)
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#define VMX_PROCBASED_CTLS2_INVPCID (1U<<12U)
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#define VMX_PROCBASED_CTLS2_VM_FUNCS (1U<<13U)
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#define VMX_PROCBASED_CTLS2_VMCS_SHADW (1U<<14U)
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#define VMX_PROCBASED_CTLS2_RDSEED (1U<<16U)
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#define VMX_PROCBASED_CTLS2_EPT_VE (1U<<18U)
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#define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1U<<20U)
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/* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */
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#define VMX_EPT_EXECUTE_ONLY (1U << 0)
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#define VMX_EPT_PAGE_WALK_4 (1U << 6)
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#define VMX_EPT_PAGE_WALK_5 (1U << 7)
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#define VMX_EPTP_UC (1U << 8)
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#define VMX_EPTP_WB (1U << 14)
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#define VMX_EPT_2MB_PAGE (1U << 16)
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#define VMX_EPT_1GB_PAGE (1U << 17)
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#define VMX_EPT_INVEPT (1U << 20)
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#define VMX_EPT_AD (1U << 21)
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#define VMX_EPT_INVEPT_SINGLE_CONTEXT (1U << 25)
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#define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1U << 26)
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#define VMX_EPT_EXECUTE_ONLY (1U << 0U)
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#define VMX_EPT_PAGE_WALK_4 (1U << 6U)
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#define VMX_EPT_PAGE_WALK_5 (1U << 7U)
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#define VMX_EPTP_UC (1U << 8U)
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#define VMX_EPTP_WB (1U << 14U)
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#define VMX_EPT_2MB_PAGE (1U << 16U)
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#define VMX_EPT_1GB_PAGE (1U << 17U)
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#define VMX_EPT_INVEPT (1U << 20U)
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#define VMX_EPT_AD (1U << 21U)
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#define VMX_EPT_INVEPT_SINGLE_CONTEXT (1U << 25U)
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#define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1U << 26U)
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#define VMX_MIN_NR_VPID 1U
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#define VMX_MAX_NR_VPID (1U << 5)
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#define VMX_MIN_NR_VPID 1U
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#define VMX_MAX_NR_VPID (1U << 5U)
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#define VMX_VPID_TYPE_INDIVIDUAL_ADDR 0UL
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#define VMX_VPID_TYPE_SINGLE_CONTEXT 1UL
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#define VMX_VPID_TYPE_ALL_CONTEXT 2UL
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#define VMX_VPID_TYPE_SINGLE_NON_GLOBAL 3UL
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#define VMX_VPID_INVVPID (1U << 0) /* (32 - 32) */
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#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1U << 8) /* (40 - 32) */
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#define VMX_VPID_INVVPID_SINGLE_CONTEXT (1U << 9) /* (41 - 32) */
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#define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1U << 10) /* (42 - 32) */
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#define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1U << 11) /* (43 - 32) */
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#define VMX_VPID_INVVPID (1U << 0U) /* (32 - 32) */
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#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1U << 8U) /* (40 - 32) */
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#define VMX_VPID_INVVPID_SINGLE_CONTEXT (1U << 9U) /* (41 - 32) */
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#define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1U << 10U) /* (42 - 32) */
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#define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1U << 11U) /* (43 - 32) */
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#define VMX_EPT_MT_EPTE_SHIFT 3
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#define VMX_EPT_MT_EPTE_SHIFT 3U
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#define VMX_EPTP_PWL_MASK 0x38UL
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#define VMX_EPTP_PWL_4 0x18UL
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#define VMX_EPTP_PWL_5 0x20UL
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#define VMX_EPTP_AD_ENABLE_BIT (1UL << 6)
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#define VMX_EPTP_PWL_4 0x18UL
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#define VMX_EPTP_PWL_5 0x20UL
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#define VMX_EPTP_AD_ENABLE_BIT (1UL << 6U)
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#define VMX_EPTP_MT_MASK 0x7UL
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#define VMX_EPTP_MT_WB 0x6UL
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#define VMX_EPTP_MT_UC 0x0UL
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#define VMX_EPTP_MT_WB 0x6UL
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#define VMX_EPTP_MT_UC 0x0UL
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/* VMX exit control bits */
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#define VMX_EXIT_CTLS_SAVE_DBG (1U<<2)
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#define VMX_EXIT_CTLS_HOST_ADDR64 (1U<<9)
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#define VMX_EXIT_CTLS_LOAD_PERF (1U<<12)
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#define VMX_EXIT_CTLS_ACK_IRQ (1U<<15)
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#define VMX_EXIT_CTLS_SAVE_PAT (1U<<18)
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#define VMX_EXIT_CTLS_LOAD_PAT (1U<<19)
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#define VMX_EXIT_CTLS_SAVE_EFER (1U<<20)
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#define VMX_EXIT_CTLS_LOAD_EFER (1U<<21)
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#define VMX_EXIT_CTLS_SAVE_PTMR (1U<<22)
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#define VMX_EXIT_CTLS_SAVE_DBG (1U<<2U)
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#define VMX_EXIT_CTLS_HOST_ADDR64 (1U<<9U)
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#define VMX_EXIT_CTLS_LOAD_PERF (1U<<12U)
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#define VMX_EXIT_CTLS_ACK_IRQ (1U<<15U)
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#define VMX_EXIT_CTLS_SAVE_PAT (1U<<18U)
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#define VMX_EXIT_CTLS_LOAD_PAT (1U<<19U)
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#define VMX_EXIT_CTLS_SAVE_EFER (1U<<20U)
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#define VMX_EXIT_CTLS_LOAD_EFER (1U<<21U)
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#define VMX_EXIT_CTLS_SAVE_PTMR (1U<<22U)
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/* VMX entry control bits */
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#define VMX_ENTRY_CTLS_LOAD_DBG (1U<<2)
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#define VMX_ENTRY_CTLS_IA32E_MODE (1U<<9)
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#define VMX_ENTRY_CTLS_ENTRY_SMM (1U<<10)
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#define VMX_ENTRY_CTLS_DEACT_DUAL (1U<<11)
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#define VMX_ENTRY_CTLS_LOAD_PERF (1U<<13)
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#define VMX_ENTRY_CTLS_LOAD_PAT (1U<<14)
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#define VMX_ENTRY_CTLS_LOAD_EFER (1U<<15)
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#define VMX_ENTRY_CTLS_LOAD_DBG (1U<<2U)
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#define VMX_ENTRY_CTLS_IA32E_MODE (1U<<9U)
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#define VMX_ENTRY_CTLS_ENTRY_SMM (1U<<10U)
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#define VMX_ENTRY_CTLS_DEACT_DUAL (1U<<11U)
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#define VMX_ENTRY_CTLS_LOAD_PERF (1U<<13U)
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#define VMX_ENTRY_CTLS_LOAD_PAT (1U<<14U)
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#define VMX_ENTRY_CTLS_LOAD_EFER (1U<<15U)
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/* VMX entry/exit Interrupt info */
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#define VMX_INT_INFO_ERR_CODE_VALID (1U<<11)
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#define VMX_INT_INFO_VALID (1U<<31)
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#define VMX_INT_INFO_ERR_CODE_VALID (1U<<11U)
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#define VMX_INT_INFO_VALID (1U<<31U)
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#define VMX_INT_TYPE_MASK (0x700U)
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#define VMX_INT_TYPE_EXT_INT 0U
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#define VMX_INT_TYPE_NMI 2U
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@ -406,9 +406,9 @@ static inline uint64_t apic_access_offset(uint64_t qual)
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return (qual & 0xFFFUL);
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}
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#define RFLAGS_C (1U<<0)
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#define RFLAGS_Z (1U<<6)
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#define RFLAGS_AC (1U<<18)
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#define RFLAGS_C (1U<<0U)
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#define RFLAGS_Z (1U<<6U)
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#define RFLAGS_AC (1U<<18U)
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/* CR0 bits hv want to trap to track status change */
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#define CR0_TRAP_MASK (CR0_PE | CR0_PG | CR0_WP | CR0_CD | CR0_NW )
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@ -424,7 +424,7 @@ static inline uint64_t apic_access_offset(uint64_t qual)
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CR4_OSXMMEXCPT | CR4_SMAP | CR4_PKE | \
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CR4_SMXE | CR4_UMIP )
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#define VMX_SUPPORT_UNRESTRICTED_GUEST (1U<<5)
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#define VMX_SUPPORT_UNRESTRICTED_GUEST (1U<<5U)
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/* External Interfaces */
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void exec_vmxon_instr(uint16_t pcpu_id);
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