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hv: Write Buffer Flush - VT-d

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This patch does the following changes
According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers
are flushed implicitly upon Remapping Hardware Caches Invalidation even on
platforms that set RWBF to 1 in capability register. So removed write buffer
flushing as current ACRN issues cache invalidation commands in all cases.

Tracked-On: #1855
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
This commit is contained in:
Sainath Grandhi
2018-12-23 00:17:04 -08:00
committed by wenlingz
parent a5113d922d
commit ef03385f42
2 changed files with 5 additions and 22 deletions
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5
hypervisor/include/arch/x86/vtd.h
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@@ -129,11 +129,6 @@ static inline uint8_t iommu_cap_plmr(uint64_t cap)
return ((uint8_t)(cap >> 5U) & 1U);
}
static inline uint8_t iommu_cap_rwbf(uint64_t cap)
{
return ((uint8_t)(cap >> 4U) & 1U);
}
static inline uint8_t iommu_cap_afl(uint64_t cap)
{
return ((uint8_t)(cap >> 3U) & 1U);