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hv: Let trampoline execution use 1GB pages

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ACRN currently uses 2MB large pages in the page tables setup
for trampoline code and data. This patch lets ACRN use 1GB large
pages instead.
When it comes to fixing symbols in trampoline code, fixing pointers
in PDPT is no more needed as PDPT PTEs contain Physical Address.

Tracked-On: #3899
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Sainath Grandhi
2019-10-08 16:59:51 -07:00
committed by wenlingz
parent 70f2ee398b
commit f01aad7e77
2 changed files with 8 additions and 20 deletions
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19
hypervisor/arch/x86/boot/trampoline.S
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@@ -179,7 +179,8 @@ trampoline_gdt_ptr:
.short (trampoline_gdt_end - trampoline_gdt) - 1
.quad trampoline_gdt
/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
/* PML4 and PDPT tables initialized to map first 4 GBytes of memory */
/* Assumes CPU supports 1GB large pages */
.align 4
.global cpu_boot_page_tables_ptr
cpu_boot_page_tables_ptr:
@@ -197,19 +198,9 @@ cpu_boot_page_tables_start:
trampoline_pdpt_addr:
address = 0
.rept 4
/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad trampoline_pdt_addr + address + 0x3
/*0x1000 = PAGE_SIZE*/
address = address + 0x1000
.endr
/*0x1000 = PAGE_SIZE*/
.align 0x1000
trampoline_pdt_addr:
address = 0
.rept 2048
/* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */
.quad address + 0x83
address = address + 0x200000
/* 0x83 = (PAGE_PRESENT | PAGE_PSE | PAGE_RW) */
.quad address + 0x83
address = address + 0x40000000
.endr
.end