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hv: fix Violations touched ACRN Coding Guidelines

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fix violations touched below:
1.Cast operation on a constant value
2.signed/unsigned implicity conversion
3.return value unused.

V1->V2:
1.bitmap api will return boolean type, not need to check "!= 0", deleted.
2.The behaves ~(uint32_t)X and (uint32_t)~X are not defined in ACRN hypervisor Coding Guidelines,
removed the change of it.
Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
huihuang.shi
2019-08-14 16:34:29 +08:00
committed by ACRN System Integration
parent f1b71d983a
commit f147c388a5
12 changed files with 31 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/arch/x86/guest/assign.c
View File

@@ -520,7 +520,7 @@ static void ptirq_handle_intx(struct acrn_vm *vm,
void ptirq_softirq(uint16_t pcpu_id)
{
struct acrn_vcpu *vcpu = (struct acrn_vcpu *)per_cpu(vcpu, pcpu_id);
struct acrn_vcpu *vcpu = per_cpu(vcpu, pcpu_id);
struct acrn_vm *vm = vcpu->vm;
while (1) {

4
hypervisor/arch/x86/guest/instr_emul.c
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@@ -573,8 +573,8 @@ static void vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum cpu_reg_name seg,
* In 64-bit mode all segments except %fs and %gs have a segment
* base address of 0.
*/
if (cpu_mode == CPU_MODE_64BIT && seg != CPU_REG_FS &&
seg != CPU_REG_GS) {
if ((cpu_mode == CPU_MODE_64BIT) && (seg != CPU_REG_FS) &&
(seg != CPU_REG_GS)) {
segbase = 0UL;
} else {
segbase = desc->base;

2
hypervisor/arch/x86/guest/pm.c
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@@ -39,7 +39,7 @@ int32_t validate_pstate(const struct acrn_vm *vm, uint64_t perf_ctl)
max_px_ctl_val = ((px_data[0].control & 0xff00UL) >> 8U);
/* get min px control value, should be for p(px_cnt-1), i.e. LFM. */
min_px_ctl_val = ((px_data[px_cnt - 1].control & 0xff00UL) >> 8U);
min_px_ctl_val = ((px_data[px_cnt - 1U].control & 0xff00UL) >> 8U);
px_target_val = ((perf_ctl & 0xff00UL) >> 8U);
if ((px_target_val <= max_px_ctl_val) && (px_target_val >= min_px_ctl_val)) {

12
hypervisor/arch/x86/guest/vcpu.c
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@@ -67,9 +67,9 @@ void vcpu_set_rip(struct acrn_vcpu *vcpu, uint64_t val)
bitmap_set_lock(CPU_REG_RIP, &vcpu->reg_updated);
}
uint64_t vcpu_get_rsp(struct acrn_vcpu *vcpu)
uint64_t vcpu_get_rsp(const struct acrn_vcpu *vcpu)
{
struct run_context *ctx =
const struct run_context *ctx =
&vcpu->arch.contexts[vcpu->arch.cur_context].run_ctx;
return ctx->guest_cpu_regs.regs.rsp;
@@ -147,7 +147,7 @@ void vcpu_set_guest_msr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t val)
/*
* Write the eoi_exit_bitmaps to VMCS fields
*/
void vcpu_set_vmcs_eoi_exit(struct acrn_vcpu *vcpu)
void vcpu_set_vmcs_eoi_exit(const struct acrn_vcpu *vcpu)
{
pr_dbg("%s", __func__);
@@ -474,8 +474,9 @@ int32_t run_vcpu(struct acrn_vcpu *vcpu)
pr_info("VM %d Starting VCPU %hu",
vcpu->vm->vm_id, vcpu->vcpu_id);
if (vcpu->arch.vpid != 0U)
if (vcpu->arch.vpid != 0U) {
exec_vmwrite16(VMX_VPID, vcpu->arch.vpid);
}
/*
* A power-up or a reset invalidates all linear mappings,
@@ -491,8 +492,9 @@ int32_t run_vcpu(struct acrn_vcpu *vcpu)
* currently, there is no other place to do vmcs switch
* Please add IBPB set for future vmcs switch case(like trusty)
*/
if (ibrs_type == IBRS_RAW)
if (ibrs_type == IBRS_RAW) {
msr_write(MSR_IA32_PRED_CMD, PRED_SET_IBPB);
}
#ifdef CONFIG_L1D_FLUSH_VMENTRY_ENABLED
cpu_l1d_flush();

3
hypervisor/arch/x86/guest/vlapic.c
View File

@@ -2138,7 +2138,7 @@ int32_t vlapic_x2apic_write(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t val)
return error;
}
int32_t vlapic_create(struct acrn_vcpu *vcpu)
void vlapic_create(struct acrn_vcpu *vcpu)
{
vcpu->arch.vlapic.vm = vcpu->vm;
vcpu->arch.vlapic.vcpu = vcpu;
@@ -2159,7 +2159,6 @@ int32_t vlapic_create(struct acrn_vcpu *vcpu)
}
vlapic_init(vcpu_vlapic(vcpu));
return 0;
}
/*