diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h b/misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h index 05426ddcc..28c09a7db 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h @@ -1,8 +1,9 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef IVSHMEM_CFG_H #define IVSHMEM_CFG_H diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h b/misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h index 6a244f6d3..e68de378b 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,77 +7,48 @@ #ifndef MISC_CFG_H #define MISC_CFG_H -#define SOS_ROOTFS "root=/dev/sda3 " -#define SOS_CONSOLE "console=ttyS0 " -#define SOS_COM1_BASE 0x3F8U -#define SOS_COM1_IRQ 4U -#define SOS_COM2_BASE 0x2F8U -#define SOS_COM2_IRQ 5U - -#define SOS_BOOTARGS_DIFF "rw " \ - "rootwait " \ - "console=tty0 " \ - "consoleblank=0 " \ - "no_timer_check " \ - "quiet " \ - "loglevel=3 " \ - "i915.nuclear_pageflip=1 " \ - "swiotlb=131072 " \ - "maxcpus=3" - -#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U)) - -#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U)) -#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) +#define SOS_ROOTFS "root=/dev/sda3" +#define SOS_CONSOLE "console=ttyS0" +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 4U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 5U +#define SOS_BOOTARGS_DIFF \ + "rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \ + "swiotlb=131072 maxcpus=3" +#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U)) +#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U)) +#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) #ifdef CONFIG_RDT_ENABLED - -/* - * The maximum CLOS that is allowed by ACRN hypervisor, - * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) - * among all supported RDT resources in the platform. In other words, it is - * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent - * CLOS allocations between all the RDT resources. - */ -#define HV_SUPPORTED_MAX_CLOS 0U - -/* - * Max number of Cache Mask entries corresponding to each CLOS. - * This can vary if CDP is enabled vs disabled, as each CLOS entry - * will have corresponding cache mask values for Data and Code when - * CDP is enabled. - */ -#define MAX_MBA_CLOS_NUM_ENTRIES 0U - -/* Max number of MBA delay entries corresponding to each CLOS. */ -#define MAX_CACHE_CLOS_NUM_ENTRIES 0U - -#define CLOS_MASK_0 0xfffU -#define CLOS_MASK_1 0xfffU -#define CLOS_MASK_2 0xfffU -#define CLOS_MASK_3 0xfffU -#define CLOS_MASK_4 0xfffU -#define CLOS_MASK_5 0xfffU -#define CLOS_MASK_6 0xfffU -#define CLOS_MASK_7 0xfffU -#define CLOS_MASK_8 0xfffU -#define CLOS_MASK_9 0xfffU -#define CLOS_MASK_10 0xfffU -#define CLOS_MASK_11 0xfffU -#define CLOS_MASK_12 0xfffU -#define CLOS_MASK_13 0xfffU -#define CLOS_MASK_14 0xfffU -#define CLOS_MASK_15 0xfffU - -#define VM0_VCPU_CLOS {0U} -#define VM1_VCPU_CLOS {0U, 0U, 0U} -#define VM2_VCPU_CLOS {0U} +#define HV_SUPPORTED_MAX_CLOS 0U +#define MAX_MBA_CLOS_NUM_ENTRIES 0U +#define MAX_CACHE_CLOS_NUM_ENTRIES 0U +#define MBA_MASK_0 0U +#define CLOS_MASK_0 0xfffU +#define CLOS_MASK_1 0xfffU +#define CLOS_MASK_2 0xfffU +#define CLOS_MASK_3 0xfffU +#define CLOS_MASK_4 0xfffU +#define CLOS_MASK_5 0xfffU +#define CLOS_MASK_6 0xfffU +#define CLOS_MASK_7 0xfffU +#define CLOS_MASK_8 0xfffU +#define CLOS_MASK_9 0xfffU +#define CLOS_MASK_10 0xfffU +#define CLOS_MASK_11 0xfffU +#define CLOS_MASK_12 0xfffU +#define CLOS_MASK_13 0xfffU +#define CLOS_MASK_14 0xfffU +#define CLOS_MASK_15 0xfffU +#define VM0_VCPU_CLOS \ + { 0U } +#define VM1_VCPU_CLOS \ + { 0U, 0U, 0U } +#define VM2_VCPU_CLOS \ + { 0U } #endif - -#define VM0_BOOT_ARGS "reboot=acpi" - - -#define VM0_PT_INTX_NUM 0U +#define VM0_PT_INTX_NUM 0U #endif /* MISC_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c b/misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c index 3ae881679..d6cca39a6 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c @@ -4,11 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include #include #include #include -#include -#include +#include +#include struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c b/misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c index 021123bb1..b3c925a7c 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c @@ -1,10 +1,8 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ -#include - +#include struct pt_intx_config vm0_pt_intx[1U]; - diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h b/misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h index 0de250f18..1ae0122e7 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h @@ -7,75 +7,68 @@ #ifndef VBAR_BASE_H_ #define VBAR_BASE_H_ -#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \ - .vbar_base[2] = HI_MMIO_START + 0x0UL +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL -#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL -#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL +#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL -#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL -#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL -#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL -#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL +#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL -#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL +#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL -#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL +#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL -#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL +#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL -#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL +#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL -#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL +#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL -#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL +#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL -#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \ - .vbar_base[1] = 0x80000000UL +#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL -#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL -#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL -#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL +#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL -#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL +#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL -#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL +#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL -#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL +#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL -#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL -#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \ - .vbar_base[2] = 0x834e7000UL +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL -#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \ - .vbar_base[1] = 0x834f6000UL, \ - .vbar_base[5] = 0x834f5000UL +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL -#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL -#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL +#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL -#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL +#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL -#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL -#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL -#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \ - .vbar_base[2] = 0x834f2000UL +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL -#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \ - .vbar_base[4] = 0x83200000UL +#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL -#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL +#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL -#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL #endif /* VBAR_BASE_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c b/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c index bf9052980..bb1350cc7 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c @@ -1,121 +1,133 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ -#include + +#include #include -#include - +#include extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; - extern struct pt_intx_config vm0_pt_intx[1U]; - struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { - { /* VM0 */ + { + /* VM0 */ CONFIG_SAFETY_VM(1), .name = "ACRN PRE-LAUNCHED VM0", - .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, .guest_flags = 0UL, #ifdef CONFIG_RDT_ENABLED .clos = VM0_VCPU_CLOS, #endif - .memory = { - .start_hpa = VM0_CONFIG_MEM_START_HPA, - .size = VM0_CONFIG_MEM_SIZE, - .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, - .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, - }, - .os_config = { - .name = "Zephyr", - .kernel_type = KERNEL_ZEPHYR, - .kernel_mod_tag = "Zephyr_RawImage", - .kernel_load_addr = 0x8000, - .kernel_entry_addr = 0x8000, - .bootargs = VM0_BOOT_ARGS, - }, - .acpi_config = { - .acpi_mod_tag = "ACPI_VM0", - }, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM2_BASE, - .irq = COM2_IRQ, - .t_vuart.vm_id = 1U, - .t_vuart.vuart_id = 1U, - }, + .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, + .memory = + { + .start_hpa = VM0_CONFIG_MEM_START_HPA, + .size = VM0_CONFIG_MEM_SIZE, + .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, + .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, + }, + .os_config = + { + .name = "Zephyr", + .kernel_type = KERNEL_ZEPHYR, + .kernel_mod_tag = "Zephyr_RawImage", + .kernel_load_addr = 0x8000, + .kernel_entry_addr = 0x8000, + }, + .acpi_config = + { + .acpi_mod_tag = "ACPI_VM0", + }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 1U, + .t_vuart.vuart_id = 1U, + }, #ifdef VM0_PASSTHROUGH_TPM .pt_tpm2 = true, - .mmiodevs[0] = { - .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, - .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, - .size = VM0_TPM_BUFFER_SIZE, - }, + .mmiodevs[0] = + { + .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, + .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, + .size = VM0_TPM_BUFFER_SIZE, + }, #endif #ifdef P2SB_BAR_ADDR .pt_p2sb_bar = true, - .mmiodevs[0] = { - .base_gpa = P2SB_BAR_ADDR_GPA, - .base_hpa = P2SB_BAR_ADDR, - .size = P2SB_BAR_SIZE, - }, + .mmiodevs[0] = + { + .base_gpa = P2SB_BAR_ADDR_GPA, + .base_hpa = P2SB_BAR_ADDR, + .size = P2SB_BAR_SIZE, + }, #endif .pt_intx_num = VM0_PT_INTX_NUM, .pt_intx = &vm0_pt_intx[0U], }, - { /* VM1 */ + { + /* VM1 */ CONFIG_SOS_VM, .name = "ACRN SOS VM", - - /* Allow SOS to reboot the host since there is supposed to be the highest severity guest */ + /* Allow Service VM to reboot the system since it is the highest priority VM. */ .guest_flags = 0UL, #ifdef CONFIG_RDT_ENABLED .clos = VM1_VCPU_CLOS, #endif .cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY, - .memory = { - .start_hpa = 0UL, - }, - .os_config = { - .name = "ACRN Service OS", - .kernel_type = KERNEL_BZIMAGE, - .kernel_mod_tag = "Linux_bzImage", - .bootargs = SOS_VM_BOOTARGS, - }, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = SOS_COM1_BASE, - .irq = SOS_COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = SOS_COM2_BASE, - .irq = SOS_COM2_IRQ, - .t_vuart.vm_id = 0U, - .t_vuart.vuart_id = 1U, - }, + .memory = + { + .start_hpa = 0UL, + }, + .os_config = + { + .name = "ACRN Service OS", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = SOS_VM_BOOTARGS, + }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM1_BASE, + .irq = SOS_COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM2_BASE, + .irq = SOS_COM2_IRQ, + .t_vuart.vm_id = 0U, + .t_vuart.vuart_id = 1U, + }, .pci_dev_num = 0U, .pci_devs = sos_pci_devs, }, - { /* VM2 */ + { + /* VM2 */ CONFIG_POST_STD_VM(1), #ifdef CONFIG_RDT_ENABLED .clos = VM2_VCPU_CLOS, #endif .cpu_affinity = VM2_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, }, }; diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h b/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h index 62017c7b7..fa3fe3ec0 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h @@ -1,36 +1,29 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef VM_CONFIGURATIONS_H #define VM_CONFIGURATIONS_H #include #include - -/* SOS_VM_NUM can only be 0U or 1U; - * When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; - * MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM; - */ -#define PRE_VM_NUM 1U -#define SOS_VM_NUM 1U -#define MAX_POST_VM_NUM 1U -#define CONFIG_MAX_KATA_VM_NUM 0U - -/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */ -#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \ - GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING) - -#define VM0_CONFIG_MEM_START_HPA 0x100000000UL -#define VM0_CONFIG_MEM_SIZE 0x20000000UL -#define VM0_CONFIG_MEM_START_HPA2 0x0UL -#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL - +/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be + * bigger than CONFIG_MAX_KATA_VM_NUM. */ +#define PRE_VM_NUM 1U +#define SOS_VM_NUM 1U +#define MAX_POST_VM_NUM 1U +#define CONFIG_MAX_KATA_VM_NUM 0U +/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */ +#define DM_OWNED_GUEST_FLAG_MASK \ + (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \ + GUEST_FLAG_IO_COMPLETION_POLLING) +#define VM0_CONFIG_MEM_START_HPA 0x100000000UL +#define VM0_CONFIG_MEM_SIZE 0x20000000UL +#define VM0_CONFIG_MEM_START_HPA2 0x0UL +#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL /* SOS_VM == VM1 */ -#define SOS_VM_BOOTARGS SOS_ROOTFS \ - SOS_CONSOLE \ - SOS_IDLE \ - SOS_BOOTARGS_DIFF +#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF #endif /* VM_CONFIGURATIONS_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ivshmem_cfg.h b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ivshmem_cfg.h index e5e2c2a7e..efb1f36de 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ivshmem_cfg.h +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ivshmem_cfg.h @@ -1,28 +1,25 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef IVSHMEM_CFG_H #define IVSHMEM_CFG_H #include -#include - -#define IVSHMEM_SHM_REGION_0 "hv:/shm_region_0" - -/* - * The IVSHMEM_SHM_SIZE is the sum of all memory regions. - * The size range of each memory region is [2MB, 512MB] and is a power of 2. - */ -#define IVSHMEM_SHM_SIZE 0x200000UL -#define IVSHMEM_DEV_NUM 2UL +#include +#define IVSHMEM_SHM_REGION_0 "hv:/shm_region_0" +/* The IVSHMEM_SHM_SIZE is the sum of all memory regions. The size range of each memory region is [2MB, 512MB] and is a + * power of 2. */ +#define IVSHMEM_SHM_SIZE 0x200000UL +#define IVSHMEM_DEV_NUM 2UL /* All user defined memory regions */ -#define IVSHMEM_SHM_REGIONS \ - { \ - .name = IVSHMEM_SHM_REGION_0, \ - .size = 0x200000UL, /* 2M */ \ +#define IVSHMEM_SHM_REGIONS \ + { \ + .name = IVSHMEM_SHM_REGION_0, \ + .size = 0x200000UL, \ }, #endif /* IVSHMEM_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/misc_cfg.h b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/misc_cfg.h index d74ec2679..7d9f91517 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/misc_cfg.h +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/misc_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,87 +7,58 @@ #ifndef MISC_CFG_H #define MISC_CFG_H -#define SOS_ROOTFS "root=/dev/nvme0n1p3 " -#define SOS_CONSOLE "console=ttyS0 " -#define SOS_COM1_BASE 0x3F8U -#define SOS_COM1_IRQ 4U -#define SOS_COM2_BASE 0x2F8U -#define SOS_COM2_IRQ 5U - -#define SOS_BOOTARGS_DIFF "rw " \ - "rootwait " \ - "console=tty0 " \ - "consoleblank=0 " \ - "no_timer_check " \ - "quiet " \ - "loglevel=3 " \ - "i915.nuclear_pageflip=1 " \ - "swiotlb=131072 " \ - "maxcpus=2" - -#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) - -#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) -#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) -#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U)) +#define SOS_ROOTFS "root=/dev/nvme0n1p3" +#define SOS_CONSOLE "console=ttyS0" +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 4U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 5U +#define SOS_BOOTARGS_DIFF \ + "rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \ + "swiotlb=131072 maxcpus=2" +#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) +#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED - -/* - * The maximum CLOS that is allowed by ACRN hypervisor, - * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) - * among all supported RDT resources in the platform. In other words, it is - * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent - * CLOS allocations between all the RDT resources. - */ -#define HV_SUPPORTED_MAX_CLOS 0U - -/* - * Max number of Cache Mask entries corresponding to each CLOS. - * This can vary if CDP is enabled vs disabled, as each CLOS entry - * will have corresponding cache mask values for Data and Code when - * CDP is enabled. - */ -#define MAX_MBA_CLOS_NUM_ENTRIES 0U - -/* Max number of MBA delay entries corresponding to each CLOS. */ -#define MAX_CACHE_CLOS_NUM_ENTRIES 0U - -#define CLOS_MASK_0 0xfffU -#define CLOS_MASK_1 0xfffU -#define CLOS_MASK_2 0xfffU -#define CLOS_MASK_3 0xfffU -#define CLOS_MASK_4 0xfffU -#define CLOS_MASK_5 0xfffU -#define CLOS_MASK_6 0xfffU -#define CLOS_MASK_7 0xfffU -#define CLOS_MASK_8 0xfffU -#define CLOS_MASK_9 0xfffU -#define CLOS_MASK_10 0xfffU -#define CLOS_MASK_11 0xfffU -#define CLOS_MASK_12 0xfffU -#define CLOS_MASK_13 0xfffU -#define CLOS_MASK_14 0xfffU -#define CLOS_MASK_15 0xfffU - -#define VM0_VCPU_CLOS {0U, 0U} -#define VM1_VCPU_CLOS {0U, 0U} -#define VM2_VCPU_CLOS {0U, 0U} -#define VM3_VCPU_CLOS {0U} +#define HV_SUPPORTED_MAX_CLOS 0U +#define MAX_MBA_CLOS_NUM_ENTRIES 0U +#define MAX_CACHE_CLOS_NUM_ENTRIES 0U +#define MBA_MASK_0 0U +#define CLOS_MASK_0 0xfffU +#define CLOS_MASK_1 0xfffU +#define CLOS_MASK_2 0xfffU +#define CLOS_MASK_3 0xfffU +#define CLOS_MASK_4 0xfffU +#define CLOS_MASK_5 0xfffU +#define CLOS_MASK_6 0xfffU +#define CLOS_MASK_7 0xfffU +#define CLOS_MASK_8 0xfffU +#define CLOS_MASK_9 0xfffU +#define CLOS_MASK_10 0xfffU +#define CLOS_MASK_11 0xfffU +#define CLOS_MASK_12 0xfffU +#define CLOS_MASK_13 0xfffU +#define CLOS_MASK_14 0xfffU +#define CLOS_MASK_15 0xfffU +#define VM0_VCPU_CLOS \ + { 0U, 0U } +#define VM1_VCPU_CLOS \ + { 0U, 0U } +#define VM2_VCPU_CLOS \ + { 0U, 0U } +#define VM3_VCPU_CLOS \ + { 0U } #endif +#define VM0_CONFIG_PCI_DEV_NUM 4U +#define VM2_CONFIG_PCI_DEV_NUM 1U -#define VM0_CONFIG_PCI_DEV_NUM 4U -#define VM2_CONFIG_PCI_DEV_NUM 1U - -#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 no_ipi_broadcast=1 \ -console=ttyS0 noxsave nohpet no_timer_check \ -ignore_loglevel consoleblank=0 tsc=reliable clocksource=tsc \ -x2apic_phys processor.max_cstate=0 intel_idle.max_cstate=0 intel_pstate=disable \ -mce=ignore_ce audit=0 isolcpus=nohz,domain,1 nohz_full=1 \ -rcu_nocbs=1 nosoftlockup idle=poll irqaffinity=0 \ -reboot=acpi" - - -#define VM0_PT_INTX_NUM 0U +#define VM0_BOOT_ARGS \ + "rw rootwait root=/dev/sda3 no_ipi_broadcast=1 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel " \ + "consoleblank=0 tsc=reliable clocksource=tsc x2apic_phys processor.max_cstate=0 intel_idle.max_cstate=0 " \ + "intel_pstate=disable mce=ignore_ce audit=0 isolcpus=nohz,domain,1 nohz_full=1 rcu_nocbs=1 nosoftlockup " \ + "idle=poll irqaffinity=0 reboot=acpi" +#define VM0_PT_INTX_NUM 0U #endif /* MISC_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pci_dev.c b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pci_dev.c index be1c09a8f..9fd191504 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pci_dev.c +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pci_dev.c @@ -4,19 +4,19 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include #include #include #include -#include -#include +#include +#include #include /* * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for * passthrough device configuration and shm_name for ivshmem device configuration. */ -#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR +#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR /* * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops @@ -44,7 +44,7 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = { .vbdf.bits = {.b = 0x00U, .d = 0x03U, .f = 0x00U}, .vdev_ops = &vpci_ivshmem_ops, .shm_region_name = IVSHMEM_SHM_REGION_0, - IVSHMEM_DEVICE_0_VBAR + IVSHMEM_DEVICE_0_VBAR, }, }; @@ -55,6 +55,6 @@ struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM] = { .emu_type = PCI_DEV_TYPE_HVEMUL, .vbdf.value = UNASSIGNED_VBDF, .vdev_ops = &vpci_ivshmem_ops, - .shm_region_name = IVSHMEM_SHM_REGION_0 + .shm_region_name = IVSHMEM_SHM_REGION_0, }, }; diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pt_intx.c b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pt_intx.c index 021123bb1..b3c925a7c 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pt_intx.c +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pt_intx.c @@ -1,10 +1,8 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ -#include - +#include struct pt_intx_config vm0_pt_intx[1U]; - diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vbar_base.h b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vbar_base.h index 29275b0dd..b09c2d51f 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vbar_base.h +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vbar_base.h @@ -7,80 +7,70 @@ #ifndef VBAR_BASE_H_ #define VBAR_BASE_H_ -#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, \ - .vbar_base[1] = 0x80001000UL, \ - .vbar_base[2] = 0x8020000cUL +#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, .vbar_base[1] = 0x80001000UL, .vbar_base[2] = 0x8020000cUL -#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \ - .vbar_base[2] = HI_MMIO_START + 0x0UL +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL -#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL -#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL +#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL -#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL -#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL -#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL -#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL +#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL -#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL +#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL -#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL +#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL -#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL +#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL -#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL +#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL -#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL +#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL -#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL +#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL -#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \ - .vbar_base[1] = 0x80000000UL +#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL -#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL -#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL -#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL +#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL -#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL +#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL -#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL +#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL -#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL +#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL -#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL -#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \ - .vbar_base[2] = 0x834e7000UL +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL -#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \ - .vbar_base[1] = 0x834f6000UL, \ - .vbar_base[5] = 0x834f5000UL +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL -#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL -#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL +#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL -#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL +#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL -#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL -#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL, \ - .vbar_base[2] = 0x80002000UL +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL -#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \ - .vbar_base[2] = 0x834f2000UL +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL -#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \ - .vbar_base[4] = 0x83200000UL +#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL -#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL +#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL -#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL #endif /* VBAR_BASE_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.c b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.c index 7a463409c..714e9f734 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.c +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.c @@ -1,142 +1,157 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ -#include -#include -#include +#include +#include +#include extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM]; extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; extern struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM]; - extern struct pt_intx_config vm0_pt_intx[1U]; - struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { - { /* VM0 */ + { + /* VM0 */ CONFIG_PRE_RT_VM(1), .name = "ACRN PRE-LAUNCHED VM0", - .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, .guest_flags = (GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT), #ifdef CONFIG_RDT_ENABLED .clos = VM0_VCPU_CLOS, #endif - .memory = { - .start_hpa = VM0_CONFIG_MEM_START_HPA, - .size = VM0_CONFIG_MEM_SIZE, - .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, - .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, - }, - .os_config = { - .name = "PREEMPT-RT", - .kernel_type = KERNEL_BZIMAGE, - .kernel_mod_tag = "RT_bzImage", - .bootargs = VM0_BOOT_ARGS, - }, - .acpi_config = { - .acpi_mod_tag = "ACPI_VM0", - }, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM2_BASE, - .irq = COM2_IRQ, - .t_vuart.vm_id = 1U, - .t_vuart.vuart_id = 1U, - }, + .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, + .memory = + { + .start_hpa = VM0_CONFIG_MEM_START_HPA, + .size = VM0_CONFIG_MEM_SIZE, + .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, + .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, + }, + .os_config = + { + .name = "PREEMPT-RT", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "RT_bzImage", + .bootargs = VM0_BOOT_ARGS, + }, + .acpi_config = + { + .acpi_mod_tag = "ACPI_VM0", + }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 1U, + .t_vuart.vuart_id = 1U, + }, .pci_dev_num = VM0_CONFIG_PCI_DEV_NUM, .pci_devs = vm0_pci_devs, #ifdef VM0_PASSTHROUGH_TPM .pt_tpm2 = true, - .mmiodevs[0] = { - .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, - .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, - .size = VM0_TPM_BUFFER_SIZE, - }, + .mmiodevs[0] = + { + .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, + .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, + .size = VM0_TPM_BUFFER_SIZE, + }, #endif #ifdef P2SB_BAR_ADDR .pt_p2sb_bar = true, - .mmiodevs[0] = { - .base_gpa = P2SB_BAR_ADDR_GPA, - .base_hpa = P2SB_BAR_ADDR, - .size = P2SB_BAR_SIZE, - }, + .mmiodevs[0] = + { + .base_gpa = P2SB_BAR_ADDR_GPA, + .base_hpa = P2SB_BAR_ADDR, + .size = P2SB_BAR_SIZE, + }, #endif .pt_intx_num = VM0_PT_INTX_NUM, .pt_intx = &vm0_pt_intx[0U], }, - { /* VM1 */ + { + /* VM1 */ CONFIG_SOS_VM, .name = "ACRN SOS VM", - - /* Allow SOS to reboot the host since there is supposed to be the highest severity guest */ + /* Allow Service VM to reboot the system since it is the highest priority VM. */ .guest_flags = 0UL, #ifdef CONFIG_RDT_ENABLED .clos = VM1_VCPU_CLOS, #endif .cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY, - .memory = { - .start_hpa = 0UL, - }, - .os_config = { - .name = "ACRN Service OS", - .kernel_type = KERNEL_BZIMAGE, - .kernel_mod_tag = "Linux_bzImage", - .bootargs = SOS_VM_BOOTARGS, - }, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = SOS_COM1_BASE, - .irq = SOS_COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = SOS_COM2_BASE, - .irq = SOS_COM2_IRQ, - .t_vuart.vm_id = 0U, - .t_vuart.vuart_id = 1U, - }, + .memory = + { + .start_hpa = 0UL, + }, + .os_config = + { + .name = "ACRN Service OS", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = SOS_VM_BOOTARGS, + }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM1_BASE, + .irq = SOS_COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM2_BASE, + .irq = SOS_COM2_IRQ, + .t_vuart.vm_id = 0U, + .t_vuart.vuart_id = 1U, + }, .pci_dev_num = 0U, .pci_devs = sos_pci_devs, }, - { /* VM2 */ + { + /* VM2 */ CONFIG_POST_STD_VM(1), #ifdef CONFIG_RDT_ENABLED .clos = VM2_VCPU_CLOS, #endif - /* The PCI device configuration is only for in-hypervisor vPCI devices. */ + .cpu_affinity = VM2_CONFIG_CPU_AFFINITY, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, .pci_dev_num = VM2_CONFIG_PCI_DEV_NUM, .pci_devs = vm2_pci_devs, - .cpu_affinity = VM2_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, }, - { /* VM3 */ + { + /* VM3 */ CONFIG_POST_STD_VM(2), #ifdef CONFIG_RDT_ENABLED .clos = VM3_VCPU_CLOS, #endif .cpu_affinity = VM3_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, }, }; diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.h b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.h index a2c3758bf..87577faf2 100644 --- a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.h +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.h @@ -1,36 +1,29 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef VM_CONFIGURATIONS_H #define VM_CONFIGURATIONS_H #include #include - -/* SOS_VM_NUM can only be 0U or 1U; - * When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; - * MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM; - */ -#define PRE_VM_NUM 1U -#define SOS_VM_NUM 1U -#define MAX_POST_VM_NUM 2U -#define CONFIG_MAX_KATA_VM_NUM 0U - -/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */ -#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \ - GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING) - -#define VM0_CONFIG_MEM_START_HPA 0x100000000UL -#define VM0_CONFIG_MEM_SIZE 0x40000000UL -#define VM0_CONFIG_MEM_START_HPA2 0x0UL -#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL - +/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be + * bigger than CONFIG_MAX_KATA_VM_NUM. */ +#define PRE_VM_NUM 1U +#define SOS_VM_NUM 1U +#define MAX_POST_VM_NUM 2U +#define CONFIG_MAX_KATA_VM_NUM 0U +/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */ +#define DM_OWNED_GUEST_FLAG_MASK \ + (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \ + GUEST_FLAG_IO_COMPLETION_POLLING) +#define VM0_CONFIG_MEM_START_HPA 0x100000000UL +#define VM0_CONFIG_MEM_SIZE 0x40000000UL +#define VM0_CONFIG_MEM_START_HPA2 0x0UL +#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL /* SOS_VM == VM1 */ -#define SOS_VM_BOOTARGS SOS_ROOTFS \ - SOS_CONSOLE \ - SOS_IDLE \ - SOS_BOOTARGS_DIFF +#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF #endif /* VM_CONFIGURATIONS_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/industry/ivshmem_cfg.h b/misc/config_tools/data/generic_board/generic_code/industry/ivshmem_cfg.h index 05426ddcc..28c09a7db 100644 --- a/misc/config_tools/data/generic_board/generic_code/industry/ivshmem_cfg.h +++ b/misc/config_tools/data/generic_board/generic_code/industry/ivshmem_cfg.h @@ -1,8 +1,9 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef IVSHMEM_CFG_H #define IVSHMEM_CFG_H diff --git a/misc/config_tools/data/generic_board/generic_code/industry/misc_cfg.h b/misc/config_tools/data/generic_board/generic_code/industry/misc_cfg.h index fe86a6633..f23fa2b21 100644 --- a/misc/config_tools/data/generic_board/generic_code/industry/misc_cfg.h +++ b/misc/config_tools/data/generic_board/generic_code/industry/misc_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,85 +7,63 @@ #ifndef MISC_CFG_H #define MISC_CFG_H -#define SOS_ROOTFS "root=/dev/nvme0n1p3 " -#define SOS_CONSOLE "console=ttyS3 " -#define SOS_COM1_BASE 0x2E8U -#define SOS_COM1_IRQ 3U -#define SOS_COM2_BASE 0x3F8U -#define SOS_COM2_IRQ 4U - -#define SOS_BOOTARGS_DIFF "rw " \ - "rootwait " \ - "console=tty0 " \ - "consoleblank=0 " \ - "no_timer_check " \ - "quiet " \ - "loglevel=3 " \ - "i915.nuclear_pageflip=1 " \ - "swiotlb=131072 " \ - "maxcpus=4" - - -#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) -#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) -#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) -#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) -#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) -#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) -#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) -#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define SOS_ROOTFS "root=/dev/nvme0n1p3" +#define SOS_CONSOLE "console=ttyS3" +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 3U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 4U +#define SOS_BOOTARGS_DIFF \ + "rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \ + "swiotlb=131072 maxcpus=4" +#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) +#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) +#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED - -/* - * The maximum CLOS that is allowed by ACRN hypervisor, - * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) - * among all supported RDT resources in the platform. In other words, it is - * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent - * CLOS allocations between all the RDT resources. - */ -#define HV_SUPPORTED_MAX_CLOS 16U - -/* - * Max number of Cache Mask entries corresponding to each CLOS. - * This can vary if CDP is enabled vs disabled, as each CLOS entry - * will have corresponding cache mask values for Data and Code when - * CDP is enabled. - */ -#define MAX_MBA_CLOS_NUM_ENTRIES 16U - -/* Max number of MBA delay entries corresponding to each CLOS. */ -#define MAX_CACHE_CLOS_NUM_ENTRIES 16U - -#define CLOS_MASK_0 0xfffU -#define CLOS_MASK_1 0xfffU -#define CLOS_MASK_2 0xfffU -#define CLOS_MASK_3 0xfffU -#define CLOS_MASK_4 0xfffU -#define CLOS_MASK_5 0xfffU -#define CLOS_MASK_6 0xfffU -#define CLOS_MASK_7 0xfffU -#define CLOS_MASK_8 0xfffU -#define CLOS_MASK_9 0xfffU -#define CLOS_MASK_10 0xfffU -#define CLOS_MASK_11 0xfffU -#define CLOS_MASK_12 0xfffU -#define CLOS_MASK_13 0xfffU -#define CLOS_MASK_14 0xfffU -#define CLOS_MASK_15 0xfffU - -#define VM0_VCPU_CLOS {0U} -#define VM1_VCPU_CLOS {0U, 0U} -#define VM2_VCPU_CLOS {0U, 0U} -#define VM3_VCPU_CLOS {0U, 0U} -#define VM4_VCPU_CLOS {0U, 0U} -#define VM5_VCPU_CLOS {0U, 0U} -#define VM6_VCPU_CLOS {0U, 0U} -#define VM7_VCPU_CLOS {0U, 0U} +#define HV_SUPPORTED_MAX_CLOS 16U +#define MAX_MBA_CLOS_NUM_ENTRIES 16U +#define MAX_CACHE_CLOS_NUM_ENTRIES 16U +#define MBA_MASK_0 0U +#define CLOS_MASK_0 0xfffU +#define CLOS_MASK_1 0xfffU +#define CLOS_MASK_2 0xfffU +#define CLOS_MASK_3 0xfffU +#define CLOS_MASK_4 0xfffU +#define CLOS_MASK_5 0xfffU +#define CLOS_MASK_6 0xfffU +#define CLOS_MASK_7 0xfffU +#define CLOS_MASK_8 0xfffU +#define CLOS_MASK_9 0xfffU +#define CLOS_MASK_10 0xfffU +#define CLOS_MASK_11 0xfffU +#define CLOS_MASK_12 0xfffU +#define CLOS_MASK_13 0xfffU +#define CLOS_MASK_14 0xfffU +#define CLOS_MASK_15 0xfffU +#define VM0_VCPU_CLOS \ + { 0U } +#define VM1_VCPU_CLOS \ + { 0U, 0U } +#define VM2_VCPU_CLOS \ + { 0U, 0U } +#define VM3_VCPU_CLOS \ + { 0U, 0U } +#define VM4_VCPU_CLOS \ + { 0U, 0U } +#define VM5_VCPU_CLOS \ + { 0U, 0U } +#define VM6_VCPU_CLOS \ + { 0U, 0U } +#define VM7_VCPU_CLOS \ + { 0U, 0U } #endif - - -#define VM0_PT_INTX_NUM 0U +#define VM0_PT_INTX_NUM 0U #endif /* MISC_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/industry/pci_dev.c b/misc/config_tools/data/generic_board/generic_code/industry/pci_dev.c index 3ae881679..d6cca39a6 100644 --- a/misc/config_tools/data/generic_board/generic_code/industry/pci_dev.c +++ b/misc/config_tools/data/generic_board/generic_code/industry/pci_dev.c @@ -4,11 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include #include #include #include -#include -#include +#include +#include struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; diff --git a/misc/config_tools/data/generic_board/generic_code/industry/pt_intx.c b/misc/config_tools/data/generic_board/generic_code/industry/pt_intx.c index 021123bb1..b3c925a7c 100644 --- a/misc/config_tools/data/generic_board/generic_code/industry/pt_intx.c +++ b/misc/config_tools/data/generic_board/generic_code/industry/pt_intx.c @@ -1,10 +1,8 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ -#include - +#include struct pt_intx_config vm0_pt_intx[1U]; - diff --git a/misc/config_tools/data/generic_board/generic_code/industry/vbar_base.h b/misc/config_tools/data/generic_board/generic_code/industry/vbar_base.h index 0de250f18..1ae0122e7 100644 --- a/misc/config_tools/data/generic_board/generic_code/industry/vbar_base.h +++ b/misc/config_tools/data/generic_board/generic_code/industry/vbar_base.h @@ -7,75 +7,68 @@ #ifndef VBAR_BASE_H_ #define VBAR_BASE_H_ -#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \ - .vbar_base[2] = HI_MMIO_START + 0x0UL +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL -#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL -#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL +#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL -#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL -#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL -#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL -#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL +#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL -#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL +#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL -#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL +#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL -#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL +#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL -#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL +#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL -#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL +#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL -#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL +#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL -#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \ - .vbar_base[1] = 0x80000000UL +#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL -#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL -#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL -#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL +#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL -#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL +#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL -#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL +#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL -#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL +#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL -#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL -#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \ - .vbar_base[2] = 0x834e7000UL +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL -#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \ - .vbar_base[1] = 0x834f6000UL, \ - .vbar_base[5] = 0x834f5000UL +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL -#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL -#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL +#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL -#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL +#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL -#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL -#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL -#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \ - .vbar_base[2] = 0x834f2000UL +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL -#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \ - .vbar_base[4] = 0x83200000UL +#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL -#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL +#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL -#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL #endif /* VBAR_BASE_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.c b/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.c index 5f8c950a8..75bb8de17 100644 --- a/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.c +++ b/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.c @@ -1,164 +1,186 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ -#include + +#include #include -#include - +#include extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; - extern struct pt_intx_config vm0_pt_intx[1U]; - struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { - { /* VM0 */ + { + /* VM0 */ CONFIG_SOS_VM, .name = "ACRN SOS VM", - - /* Allow SOS to reboot the host since there is supposed to be the highest severity guest */ + /* Allow Service VM to reboot the system since it is the highest priority VM. */ .guest_flags = 0UL, #ifdef CONFIG_RDT_ENABLED .clos = VM0_VCPU_CLOS, #endif .cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY, - .memory = { - .start_hpa = 0UL, - }, - .os_config = { - .name = "ACRN Service OS", - .kernel_type = KERNEL_BZIMAGE, - .kernel_mod_tag = "Linux_bzImage", - .bootargs = SOS_VM_BOOTARGS, - }, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = SOS_COM1_BASE, - .irq = SOS_COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = SOS_COM2_BASE, - .irq = SOS_COM2_IRQ, - .t_vuart.vm_id = 2U, - .t_vuart.vuart_id = 1U, - }, + .memory = + { + .start_hpa = 0UL, + }, + .os_config = + { + .name = "ACRN Service OS", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = SOS_VM_BOOTARGS, + }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM1_BASE, + .irq = SOS_COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM2_BASE, + .irq = SOS_COM2_IRQ, + .t_vuart.vm_id = 2U, + .t_vuart.vuart_id = 1U, + }, .pci_dev_num = 0U, .pci_devs = sos_pci_devs, }, - { /* VM1 */ + { + /* VM1 */ CONFIG_POST_STD_VM(1), #ifdef CONFIG_RDT_ENABLED .clos = VM1_VCPU_CLOS, #endif .cpu_affinity = VM1_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, }, - { /* VM2 */ + { + /* VM2 */ CONFIG_POST_RT_VM(1), #ifdef CONFIG_RDT_ENABLED .clos = VM2_VCPU_CLOS, #endif .cpu_affinity = VM2_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM2_BASE, - .irq = COM2_IRQ, - .t_vuart.vm_id = 0U, - .t_vuart.vuart_id = 1U, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 0U, + .t_vuart.vuart_id = 1U, + }, }, - { /* VM3 */ + { + /* VM3 */ CONFIG_POST_STD_VM(2), #ifdef CONFIG_RDT_ENABLED .clos = VM3_VCPU_CLOS, #endif .cpu_affinity = VM3_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, }, - { /* VM4 */ + { + /* VM4 */ CONFIG_POST_STD_VM(3), #ifdef CONFIG_RDT_ENABLED .clos = VM4_VCPU_CLOS, #endif .cpu_affinity = VM4_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, }, - { /* VM5 */ + { + /* VM5 */ CONFIG_POST_STD_VM(4), #ifdef CONFIG_RDT_ENABLED .clos = VM5_VCPU_CLOS, #endif .cpu_affinity = VM5_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, }, - { /* VM6 */ + { + /* VM6 */ CONFIG_POST_STD_VM(5), #ifdef CONFIG_RDT_ENABLED .clos = VM6_VCPU_CLOS, #endif .cpu_affinity = VM6_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, }, - { /* VM7 */ + { + /* VM7 */ CONFIG_KATA_VM(1), #ifdef CONFIG_RDT_ENABLED .clos = VM7_VCPU_CLOS, #endif .cpu_affinity = VM7_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, }, }; diff --git a/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.h b/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.h index a9a63a3f7..a64b3b740 100644 --- a/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.h +++ b/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.h @@ -1,31 +1,25 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef VM_CONFIGURATIONS_H #define VM_CONFIGURATIONS_H #include #include - -/* SOS_VM_NUM can only be 0U or 1U; - * When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; - * MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM; - */ -#define PRE_VM_NUM 0U -#define SOS_VM_NUM 1U -#define MAX_POST_VM_NUM 7U -#define CONFIG_MAX_KATA_VM_NUM 1U - -/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */ -#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \ - GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING) - +/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be + * bigger than CONFIG_MAX_KATA_VM_NUM. */ +#define PRE_VM_NUM 0U +#define SOS_VM_NUM 1U +#define MAX_POST_VM_NUM 7U +#define CONFIG_MAX_KATA_VM_NUM 1U +/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */ +#define DM_OWNED_GUEST_FLAG_MASK \ + (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \ + GUEST_FLAG_IO_COMPLETION_POLLING) /* SOS_VM == VM0 */ -#define SOS_VM_BOOTARGS SOS_ROOTFS \ - SOS_CONSOLE \ - SOS_IDLE \ - SOS_BOOTARGS_DIFF +#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF #endif /* VM_CONFIGURATIONS_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ivshmem_cfg.h b/misc/config_tools/data/generic_board/generic_code/logical_partition/ivshmem_cfg.h index 05426ddcc..28c09a7db 100644 --- a/misc/config_tools/data/generic_board/generic_code/logical_partition/ivshmem_cfg.h +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ivshmem_cfg.h @@ -1,8 +1,9 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef IVSHMEM_CFG_H #define IVSHMEM_CFG_H diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/misc_cfg.h b/misc/config_tools/data/generic_board/generic_code/logical_partition/misc_cfg.h index 6a2732e95..f109949a9 100644 --- a/misc/config_tools/data/generic_board/generic_code/logical_partition/misc_cfg.h +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/misc_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,62 +7,41 @@ #ifndef MISC_CFG_H #define MISC_CFG_H -#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U)) -#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U)) - +#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U)) +#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U)) #ifdef CONFIG_RDT_ENABLED - -/* - * The maximum CLOS that is allowed by ACRN hypervisor, - * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) - * among all supported RDT resources in the platform. In other words, it is - * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent - * CLOS allocations between all the RDT resources. - */ -#define HV_SUPPORTED_MAX_CLOS 0U - -/* - * Max number of Cache Mask entries corresponding to each CLOS. - * This can vary if CDP is enabled vs disabled, as each CLOS entry - * will have corresponding cache mask values for Data and Code when - * CDP is enabled. - */ -#define MAX_MBA_CLOS_NUM_ENTRIES 0U - -/* Max number of MBA delay entries corresponding to each CLOS. */ -#define MAX_CACHE_CLOS_NUM_ENTRIES 0U - -#define CLOS_MASK_0 0xfffU -#define CLOS_MASK_1 0xfffU -#define CLOS_MASK_2 0xfffU -#define CLOS_MASK_3 0xfffU -#define CLOS_MASK_4 0xfffU -#define CLOS_MASK_5 0xfffU -#define CLOS_MASK_6 0xfffU -#define CLOS_MASK_7 0xfffU -#define CLOS_MASK_8 0xfffU -#define CLOS_MASK_9 0xfffU -#define CLOS_MASK_10 0xfffU -#define CLOS_MASK_11 0xfffU -#define CLOS_MASK_12 0xfffU -#define CLOS_MASK_13 0xfffU -#define CLOS_MASK_14 0xfffU -#define CLOS_MASK_15 0xfffU - -#define VM0_VCPU_CLOS {0U, 0U} -#define VM1_VCPU_CLOS {0U, 0U} +#define HV_SUPPORTED_MAX_CLOS 0U +#define MAX_MBA_CLOS_NUM_ENTRIES 0U +#define MAX_CACHE_CLOS_NUM_ENTRIES 0U +#define MBA_MASK_0 0U +#define CLOS_MASK_0 0xfffU +#define CLOS_MASK_1 0xfffU +#define CLOS_MASK_2 0xfffU +#define CLOS_MASK_3 0xfffU +#define CLOS_MASK_4 0xfffU +#define CLOS_MASK_5 0xfffU +#define CLOS_MASK_6 0xfffU +#define CLOS_MASK_7 0xfffU +#define CLOS_MASK_8 0xfffU +#define CLOS_MASK_9 0xfffU +#define CLOS_MASK_10 0xfffU +#define CLOS_MASK_11 0xfffU +#define CLOS_MASK_12 0xfffU +#define CLOS_MASK_13 0xfffU +#define CLOS_MASK_14 0xfffU +#define CLOS_MASK_15 0xfffU +#define VM0_VCPU_CLOS \ + { 0U, 0U } +#define VM1_VCPU_CLOS \ + { 0U, 0U } #endif - -#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \ -noxsave nohpet no_timer_check ignore_loglevel \ -log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi" - -#define VM1_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \ -noxsave nohpet no_timer_check ignore_loglevel \ -log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi" - - -#define VM0_PT_INTX_NUM 0U +#define VM0_BOOT_ARGS \ + "rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M " \ + "consoleblank=0 tsc=reliable reboot=acpi" +#define VM1_BOOT_ARGS \ + "rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M " \ + "consoleblank=0 tsc=reliable reboot=acpi" +#define VM0_PT_INTX_NUM 0U #endif /* MISC_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/pci_dev.c b/misc/config_tools/data/generic_board/generic_code/logical_partition/pci_dev.c index eaf709dee..12943a15e 100644 --- a/misc/config_tools/data/generic_board/generic_code/logical_partition/pci_dev.c +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/pci_dev.c @@ -4,9 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include #include #include #include -#include -#include +#include +#include diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/pt_intx.c b/misc/config_tools/data/generic_board/generic_code/logical_partition/pt_intx.c index 021123bb1..b3c925a7c 100644 --- a/misc/config_tools/data/generic_board/generic_code/logical_partition/pt_intx.c +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/pt_intx.c @@ -1,10 +1,8 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ -#include - +#include struct pt_intx_config vm0_pt_intx[1U]; - diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/vbar_base.h b/misc/config_tools/data/generic_board/generic_code/logical_partition/vbar_base.h index 0de250f18..1ae0122e7 100644 --- a/misc/config_tools/data/generic_board/generic_code/logical_partition/vbar_base.h +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/vbar_base.h @@ -7,75 +7,68 @@ #ifndef VBAR_BASE_H_ #define VBAR_BASE_H_ -#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \ - .vbar_base[2] = HI_MMIO_START + 0x0UL +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL -#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL -#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL +#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL -#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL -#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL -#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL -#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL +#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL -#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL +#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL -#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL +#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL -#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL +#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL -#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL +#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL -#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL +#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL -#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL +#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL -#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \ - .vbar_base[1] = 0x80000000UL +#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL -#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL -#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL -#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL +#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL -#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL +#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL -#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL +#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL -#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL +#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL -#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL -#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \ - .vbar_base[2] = 0x834e7000UL +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL -#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \ - .vbar_base[1] = 0x834f6000UL, \ - .vbar_base[5] = 0x834f5000UL +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL -#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL -#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL +#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL -#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL +#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL -#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL -#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL -#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \ - .vbar_base[2] = 0x834f2000UL +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL -#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \ - .vbar_base[4] = 0x83200000UL +#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL -#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL +#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL -#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL #endif /* VBAR_BASE_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.c b/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.c index bd963ec4d..6da3934c3 100644 --- a/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.c +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.c @@ -1,104 +1,116 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ -#include + +#include #include -#include - - +#include extern struct pt_intx_config vm0_pt_intx[1U]; - struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { - { /* VM0 */ + { + /* VM0 */ CONFIG_PRE_STD_VM(1), .name = "ACRN PRE-LAUNCHED VM0", - .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, .guest_flags = 0UL, #ifdef CONFIG_RDT_ENABLED .clos = VM0_VCPU_CLOS, #endif - .memory = { - .start_hpa = VM0_CONFIG_MEM_START_HPA, - .size = VM0_CONFIG_MEM_SIZE, - .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, - .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, - }, - .os_config = { - .name = "YOCTO", - .kernel_type = KERNEL_BZIMAGE, - .kernel_mod_tag = "Linux_bzImage", - .bootargs = VM0_BOOT_ARGS, - }, - .acpi_config = { - .acpi_mod_tag = "ACPI_VM0", - }, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM2_BASE, - .irq = COM2_IRQ, - .t_vuart.vm_id = 1U, - .t_vuart.vuart_id = 1U, - }, + .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, + .memory = + { + .start_hpa = VM0_CONFIG_MEM_START_HPA, + .size = VM0_CONFIG_MEM_SIZE, + .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, + .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, + }, + .os_config = + { + .name = "YOCTO", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = VM0_BOOT_ARGS, + }, + .acpi_config = + { + .acpi_mod_tag = "ACPI_VM0", + }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 1U, + .t_vuart.vuart_id = 1U, + }, #ifdef VM0_PASSTHROUGH_TPM .pt_tpm2 = true, - .mmiodevs[0] = { - .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, - .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, - .size = VM0_TPM_BUFFER_SIZE, - }, + .mmiodevs[0] = + { + .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, + .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, + .size = VM0_TPM_BUFFER_SIZE, + }, #endif #ifdef P2SB_BAR_ADDR .pt_p2sb_bar = true, - .mmiodevs[0] = { - .base_gpa = P2SB_BAR_ADDR_GPA, - .base_hpa = P2SB_BAR_ADDR, - .size = P2SB_BAR_SIZE, - }, + .mmiodevs[0] = + { + .base_gpa = P2SB_BAR_ADDR_GPA, + .base_hpa = P2SB_BAR_ADDR, + .size = P2SB_BAR_SIZE, + }, #endif .pt_intx_num = VM0_PT_INTX_NUM, .pt_intx = &vm0_pt_intx[0U], }, - { /* VM1 */ + { + /* VM1 */ CONFIG_PRE_STD_VM(2), .name = "ACRN PRE-LAUNCHED VM1", - .cpu_affinity = VM1_CONFIG_CPU_AFFINITY, .guest_flags = 0UL, #ifdef CONFIG_RDT_ENABLED .clos = VM1_VCPU_CLOS, #endif - .memory = { - .start_hpa = VM1_CONFIG_MEM_START_HPA, - .size = VM1_CONFIG_MEM_SIZE, - .start_hpa2 = VM1_CONFIG_MEM_START_HPA2, - .size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2, - }, - .os_config = { - .name = "YOCTO", - .kernel_type = KERNEL_BZIMAGE, - .kernel_mod_tag = "Linux_bzImage", - .bootargs = VM1_BOOT_ARGS, - }, - .acpi_config = { - .acpi_mod_tag = "ACPI_VM1", - }, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM2_BASE, - .irq = COM2_IRQ, - .t_vuart.vm_id = 0U, - .t_vuart.vuart_id = 1U, - }, + .cpu_affinity = VM1_CONFIG_CPU_AFFINITY, + .memory = + { + .start_hpa = VM1_CONFIG_MEM_START_HPA, + .size = VM1_CONFIG_MEM_SIZE, + .start_hpa2 = VM1_CONFIG_MEM_START_HPA2, + .size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2, + }, + .os_config = + { + .name = "YOCTO", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = VM1_BOOT_ARGS, + }, + .acpi_config = + { + .acpi_mod_tag = "ACPI_VM1", + }, + .vuart[0] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = + { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 0U, + .t_vuart.vuart_id = 1U, + }, }, }; diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.h b/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.h index cff492b90..7c3e4a7ee 100644 --- a/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.h +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.h @@ -1,33 +1,28 @@ /* - * Copyright (C) 2021 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef VM_CONFIGURATIONS_H #define VM_CONFIGURATIONS_H #include #include - -/* SOS_VM_NUM can only be 0U or 1U; - * When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; - * MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM; - */ -#define PRE_VM_NUM 2U -#define SOS_VM_NUM 0U -#define MAX_POST_VM_NUM 0U -#define CONFIG_MAX_KATA_VM_NUM 0U - -#define DM_OWNED_GUEST_FLAG_MASK 0UL - -#define VM0_CONFIG_MEM_START_HPA 0x100000000UL -#define VM0_CONFIG_MEM_SIZE 0x20000000UL -#define VM0_CONFIG_MEM_START_HPA2 0x0UL -#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL - -#define VM1_CONFIG_MEM_START_HPA 0x120000000UL -#define VM1_CONFIG_MEM_SIZE 0x20000000UL -#define VM1_CONFIG_MEM_START_HPA2 0x0UL -#define VM1_CONFIG_MEM_SIZE_HPA2 0x0UL +/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be + * bigger than CONFIG_MAX_KATA_VM_NUM. */ +#define PRE_VM_NUM 2U +#define SOS_VM_NUM 0U +#define MAX_POST_VM_NUM 0U +#define CONFIG_MAX_KATA_VM_NUM 0U +#define DM_OWNED_GUEST_FLAG_MASK 0UL +#define VM0_CONFIG_MEM_START_HPA 0x100000000UL +#define VM0_CONFIG_MEM_SIZE 0x20000000UL +#define VM0_CONFIG_MEM_START_HPA2 0x0UL +#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL +#define VM1_CONFIG_MEM_START_HPA 0x120000000UL +#define VM1_CONFIG_MEM_SIZE 0x20000000UL +#define VM1_CONFIG_MEM_START_HPA2 0x0UL +#define VM1_CONFIG_MEM_SIZE_HPA2 0x0UL #endif /* VM_CONFIGURATIONS_H */ diff --git a/misc/config_tools/data/generic_board/hybrid.xml b/misc/config_tools/data/generic_board/hybrid.xml index 932dae85f..9aa142b00 100644 --- a/misc/config_tools/data/generic_board/hybrid.xml +++ b/misc/config_tools/data/generic_board/hybrid.xml @@ -96,7 +96,7 @@ KERNEL_ZEPHYR Zephyr_RawImage - reboot=acpi + 0x8000 0x8000