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hv: don't combine the trampline code with AP start
Cleanup "cpu_secondary_xx" in the symbols/section/functions/variables name in trampline code. There is item left: the default C entry is Ap start c entry. Before ACRN enter S3, the c entry will be updated to high level S3 C entry. So s3 resume will go s3 resume path instead of AP startup path. Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Eddie Dong <Eddie.dong@intel.com>
This commit is contained in:
Yin Fengwei
lijinxia
parent
11df803da3
commit
f3831cdc80
@ -8,7 +8,7 @@
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#include <schedule.h>
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#include <version.h>
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spinlock_t cpu_secondary_spinlock = {
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spinlock_t trampline_spinlock = {
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.head = 0,
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.tail = 0
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};
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@ -574,7 +574,7 @@ void cpu_secondary_init(void)
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/* Release secondary boot spin-lock to allow one of the next CPU(s) to
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* perform this common initialization
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*/
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spinlock_release(&cpu_secondary_spinlock);
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spinlock_release(&trampline_spinlock);
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/* Initialize secondary processor interrupts. */
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interrupt_init(get_cpu_id());
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@ -615,10 +615,10 @@ void start_cpus()
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uint32_t expected_up;
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/*Copy segment for AP initialization code below 1MB */
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memcpy_s(_ld_cpu_secondary_reset_start,
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(unsigned long)&_ld_cpu_secondary_reset_size,
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_ld_cpu_secondary_reset_load,
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(unsigned long)&_ld_cpu_secondary_reset_size);
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memcpy_s(_ld_trampline_start,
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(unsigned long)&_ld_trampline_size,
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_ld_trampline_load,
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(unsigned long)&_ld_trampline_size);
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/* Set flag showing number of CPUs expected to be up to all
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* cpus
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@ -627,7 +627,7 @@ void start_cpus()
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/* Broadcast IPIs to all other CPUs */
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send_startup_ipi(INTR_CPU_STARTUP_ALL_EX_SELF,
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-1U, ((uint64_t) cpu_secondary_reset));
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-1U, ((uint64_t) trampline_start16));
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/* Wait until global count is equal to expected CPU up count or
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* configured time-out has expired
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@ -573,10 +573,10 @@ int prepare_vm0_memmap_and_e820(struct vm *vm)
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* FIXME: here using hard code GUEST_INIT_PAGE_TABLE_START as guest init page
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* table gpa start, and it will occupy at most GUEST_INIT_PT_PAGE_NUM pages.
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* Some check here:
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* - guest page table space should not override cpu_secondary_reset code area
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* - guest page table space should not override trampline code area
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* (it's a little tricky here, as under current identical mapping, HV & SOS
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* share same memory under 1M; under uefi boot mode, the defered AP startup
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* need cpu_secondary_reset code area which reserved by uefi stub keep there
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* need trampline code area which reserved by uefi stub keep there
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* no change even after SOS startup)
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* - guest page table space should not override possible RSDP fix segment
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*
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@ -604,8 +604,8 @@ uint64_t create_guest_initial_paging(struct vm *vm)
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RSDP_F_ADDR, "RSDP fix segment could be override");
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if (GUEST_INIT_PAGE_TABLE_SKIP_SIZE <
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(unsigned long)&_ld_cpu_secondary_reset_size) {
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panic("guest init PTs override cpu_secondary_reset code");
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(unsigned long)&_ld_trampline_size) {
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panic("guest init PTs override trampline code");
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}
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/* Using continuous memory for guest page tables, the total 4K page
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@ -16,12 +16,12 @@
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.extern _ld_bss_end
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.extern HOST_GDTR
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.section .cpu_secondary_reset,"ax"
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.section .trampline_reset,"ax"
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.align 4
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.code16
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.global cpu_secondary_reset
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cpu_secondary_reset:
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.global trampline_start16
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trampline_start16:
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/* Disable local interrupts */
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@ -54,14 +54,14 @@ cpu_secondary_reset:
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mov %ebx, %cr0
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/* Load temportary GDT pointer value */
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lgdt (cpu_secondary_gdt_ptr - cpu_secondary_reset)
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lgdt (trampline_gdt_ptr - trampline_start16)
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/* Perform a long jump based to start executing in 64-bit mode */
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data32 ljmp $HOST_GDT_RING0_CODE_SEL, $cpu_secondary_long_mode
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data32 ljmp $HOST_GDT_RING0_CODE_SEL, $trampline_start64
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.code64
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cpu_secondary_long_mode:
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trampline_start64:
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/* Set up all other data segment registers */
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@ -72,10 +72,8 @@ cpu_secondary_long_mode:
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mov %eax, %fs
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mov %eax, %gs
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/* Obtain secondary CPU spin-lock to serialize
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booting of secondary cores for a bit */
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spinlock_obtain(cpu_secondary_spinlock)
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/* Obtain CPU spin-lock to serialize trampline for different APs */
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spinlock_obtain(trampline_spinlock)
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/* Initialize temporary stack pointer
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NOTE: Using the PML4 memory (PDPT address is top of memory
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@ -86,51 +84,54 @@ cpu_secondary_long_mode:
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used for a VERY short period of time, so
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this reuse of PML4 memory should be acceptable. */
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movq $cpu_secondary_pdpt_addr, %rsp
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movq $trampline_pdpt_addr, %rsp
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/* Push sp magic to top of stack for call trace */
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pushq $SP_BOTTOM_MAGIC
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/* Jump to C entry for the AP */
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/* Jump to C entry */
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movq main_entry(%rip), %rax
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jmp %rax
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call cpu_secondary_init
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trampline_error: /* should never come here */
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jmp trampline_error
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cpu_secondary_error:
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/* Error condition trap */
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jmp cpu_secondary_error
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/* main entry */
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.align 8
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.global main_entry
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main_entry:
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.quad cpu_secondary_init /* default entry is AP start entry */
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/* GDT table */
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.align 4
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cpu_secondary_gdt:
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trampline_gdt:
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.quad 0x0000000000000000
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.quad 0x00af9b000000ffff
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.quad 0x00cf93000000ffff
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cpu_secondary_gdt_end:
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trampline_gdt_end:
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/* GDT pointer */
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.align 2
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cpu_secondary_gdt_ptr:
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.short (cpu_secondary_gdt_end - cpu_secondary_gdt) - 1
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.quad cpu_secondary_gdt
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trampline_gdt_ptr:
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.short (trampline_gdt_end - trampline_gdt) - 1
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.quad trampline_gdt
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/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
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.align CPU_PAGE_SIZE
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.global CPU_Boot_Page_Tables_Start
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CPU_Boot_Page_Tables_Start:
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.quad cpu_secondary_pdpt_addr + (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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.quad trampline_pdpt_addr + (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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.align CPU_PAGE_SIZE
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cpu_secondary_pdpt_addr:
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trampline_pdpt_addr:
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address = 0
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.rept 4
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.quad cpu_secondary_pdt_addr + address + \
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.quad trampline_pdt_addr + address + \
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(IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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address = address + CPU_PAGE_SIZE
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.endr
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.align CPU_PAGE_SIZE
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cpu_secondary_pdt_addr:
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trampline_pdt_addr:
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address = 0
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.rept 2048
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.quad address + (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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@ -39,20 +39,20 @@ SECTIONS
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} > ram
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_ld_cpu_secondary_reset_load = .;
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_ld_trampline_load = .;
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.cpu_secondary : AT (_ld_cpu_secondary_reset_load)
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.trampline : AT (_ld_trampline_load)
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{
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_ld_cpu_secondary_reset_start = .;
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*(.cpu_secondary_reset);
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_ld_trampline_start = .;
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*(.trampline_reset);
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. = ALIGN(4);
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_ld_cpu_secondary_reset_end = .;
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_ld_trampline_end = .;
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} > lowram
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_ld_cpu_secondary_reset_size = _ld_cpu_secondary_reset_end - _ld_cpu_secondary_reset_start;
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_ld_trampline_size = _ld_trampline_end - _ld_trampline_start;
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.data (_ld_cpu_secondary_reset_load + _ld_cpu_secondary_reset_size):
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.data (_ld_trampline_load + _ld_trampline_size):
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{
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*(.data) ;
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*(.data*) ;
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@ -156,9 +156,9 @@ int cpu_find_logical_id(uint32_t lapic_id);
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/**********************************/
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/* EXTERNAL VARIABLES */
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/**********************************/
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extern const uint8_t _ld_cpu_secondary_reset_load[];
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extern uint8_t _ld_cpu_secondary_reset_start[];
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extern const uint64_t _ld_cpu_secondary_reset_size;
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extern const uint8_t _ld_trampline_load[];
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extern uint8_t _ld_trampline_start[];
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extern const uint64_t _ld_trampline_size;
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extern uint8_t _ld_bss_start[];
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extern uint8_t _ld_bss_end[];
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@ -239,7 +239,7 @@ extern struct cpuinfo_x86 boot_cpu_data;
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/* Function prototypes */
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void cpu_dead(uint32_t logical_id);
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void cpu_secondary_reset(void);
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void trampline_start16(void);
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int hv_main(int cpu_id);
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bool is_vapic_supported(void);
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bool is_vapic_intr_delivery_supported(void);
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