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hv: self-IPI APIC register in x2APIC mode of guest vLAPIC
This patch adds support for self-IPI virtualization when guest uses vLAPIC in x2APIC mode. Tracked-On: #1626 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Reviewed-by: Xu Anthony <anthony.xu@intel.com>
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@ -2374,6 +2374,18 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
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return 0;
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return 0;
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}
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}
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static void vlapic_x2apic_self_ipi_handler(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic;
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uint32_t vector;
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struct vcpu *target_vcpu;
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lapic = &(vlapic->apic_page);
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vector = lapic->self_ipi.v & 0xFFU;
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target_vcpu = vlapic->vcpu;
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vlapic_set_intr(target_vcpu, vector, LAPIC_TRIG_EDGE);
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}
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int apic_write_vmexit_handler(struct vcpu *vcpu)
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int apic_write_vmexit_handler(struct vcpu *vcpu)
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{
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{
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uint64_t qual;
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uint64_t qual;
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@ -2428,6 +2440,11 @@ int apic_write_vmexit_handler(struct vcpu *vcpu)
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case APIC_OFFSET_TIMER_DCR:
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case APIC_OFFSET_TIMER_DCR:
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vlapic_dcr_write_handler(vlapic);
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vlapic_dcr_write_handler(vlapic);
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break;
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break;
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case APIC_OFFSET_SELF_IPI:
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if (is_x2apic_enabled(vlapic)) {
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vlapic_x2apic_self_ipi_handler(vlapic);
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}
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break;
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default:
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default:
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handled = 0;
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handled = 0;
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pr_err("Unhandled APIC-Write, offset:0x%x", offset);
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pr_err("Unhandled APIC-Write, offset:0x%x", offset);
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@ -80,6 +80,6 @@
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#define APIC_OFFSET_TIMER_ICR 0x380U /* Timer's Initial Count */
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#define APIC_OFFSET_TIMER_ICR 0x380U /* Timer's Initial Count */
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#define APIC_OFFSET_TIMER_CCR 0x390U /* Timer's Current Count */
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#define APIC_OFFSET_TIMER_CCR 0x390U /* Timer's Current Count */
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#define APIC_OFFSET_TIMER_DCR 0x3E0U /* Timer's Divide Configuration */
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#define APIC_OFFSET_TIMER_DCR 0x3E0U /* Timer's Divide Configuration */
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#define APIC_OFFSET_SELF_IPI 0x3F0U /* Self IPI Register */
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#endif /* VLAPIC_PRIV_H */
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#endif /* VLAPIC_PRIV_H */
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@ -72,7 +72,7 @@ struct lapic_regs { /*OFFSET(Hex)*/
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struct lapic_reg ccr_timer;/*390*/
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struct lapic_reg ccr_timer;/*390*/
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struct lapic_reg rsv3[4];
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struct lapic_reg rsv3[4];
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struct lapic_reg dcr_timer;/*3E0*/
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struct lapic_reg dcr_timer;/*3E0*/
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struct lapic_reg rsv4;
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struct lapic_reg self_ipi; /*3F0*/
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/*roundup sizeof current struct to 4KB*/
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/*roundup sizeof current struct to 4KB*/
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struct lapic_reg rsv5[192]; /*400 -- FF0*/
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struct lapic_reg rsv5[192]; /*400 -- FF0*/
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