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hv: vmexit: ecx should be checked instead of rcx when xsetbv

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According to SDM, xsetbv writes the contents of registers EDX:EAX into the 64-bit
extended control register (XCR) specified in the ECX register. (On processors
that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.)

In current code, RCX is checked, should ingore the high-order 32bits.

Tracked-On: #3360
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Binbin Wu 2019-07-04 10:56:42 +08:00 committed by ACRN System Integration
parent e837116691
commit f3ffce4be1
1 changed files with 2 additions and 2 deletions
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4
hypervisor/arch/x86/guest/vmexit.c
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@ -306,8 +306,8 @@ static int32_t xsetbv_vmexit_handler(struct acrn_vcpu *vcpu)
if (idx >= NR_WORLD) { if (idx >= NR_WORLD) {
ret = -1; ret = -1;
} else { } else {
/* to access XCR0,'rcx' should be 0 */ /* to access XCR0,'ecx' should be 0 */
if (vcpu_get_gpreg(vcpu, CPU_REG_RCX) != 0UL) { if ((vcpu_get_gpreg(vcpu, CPU_REG_RCX) & 0xffffffffUL) != 0UL) {
vcpu_inject_gp(vcpu, 0U); vcpu_inject_gp(vcpu, 0U);
} else { } else {
val64 = (vcpu_get_gpreg(vcpu, CPU_REG_RAX) & 0xffffffffUL) | val64 = (vcpu_get_gpreg(vcpu, CPU_REG_RAX) & 0xffffffffUL) |