diff --git a/hypervisor/include/arch/x86/asm/cpu.h b/hypervisor/include/arch/x86/asm/cpu.h
index a31f044f3..81f3fd5af 100755
--- a/hypervisor/include/arch/x86/asm/cpu.h
+++ b/hypervisor/include/arch/x86/asm/cpu.h
@@ -41,6 +41,7 @@
 #include <acrn_common.h>
 #include <asm/msr.h>
 #include <errno.h>
+#include <barrier.h>
 
 /* Define CPU stack alignment */
 #define CPU_STACK_ALIGN         16UL
@@ -565,24 +566,6 @@ static inline void cpu_sp_write(uint64_t *stack_ptr)
 	asm volatile ("movq %0, %%rsp" : : "r"(rsp));
 }
 
-/* Synchronizes all write accesses to memory */
-static inline void cpu_write_memory_barrier(void)
-{
-	asm volatile ("sfence\n" : : : "memory");
-}
-
-/* Synchronizes all read and write accesses to/from memory */
-static inline void cpu_memory_barrier(void)
-{
-	asm volatile ("mfence\n" : : : "memory");
-}
-
-/* Prevents compilers from reordering read/write access across this barrier */
-static inline void cpu_compiler_barrier(void)
-{
-	asm volatile ("" : : : "memory");
-}
-
 static inline void invlpg(unsigned long addr)
 {
 	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
diff --git a/hypervisor/include/arch/x86/asm/lib/barrier.h b/hypervisor/include/arch/x86/asm/lib/barrier.h
new file mode 100644
index 000000000..0677868ae
--- /dev/null
+++ b/hypervisor/include/arch/x86/asm/lib/barrier.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef X86_LIB_BARRIER_H
+#define X86_LIB_BARRIER_H
+/* Synchronizes all read accesses to memory */
+static inline void arch_cpu_read_memory_barrier(void)
+{
+	asm volatile ("lfence\n" : : : "memory");
+}
+
+/* Synchronizes all write accesses to memory */
+static inline void arch_cpu_write_memory_barrier(void)
+{
+	asm volatile ("sfence\n" : : : "memory");
+}
+
+/* Synchronizes all read and write accesses to/from memory */
+static inline void arch_cpu_memory_barrier(void)
+{
+	asm volatile ("mfence\n" : : : "memory");
+}
+#endif /* X86_LIB_BARRIER_H */
diff --git a/hypervisor/include/lib/barrier.h b/hypervisor/include/lib/barrier.h
new file mode 100644
index 000000000..aa020b6c5
--- /dev/null
+++ b/hypervisor/include/lib/barrier.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BARRIER_H
+#define BARRIER_H
+
+#include <types.h>
+#include <asm/lib/barrier.h>
+
+/* The mandatory functions should be implemented by arch barrier library */
+static inline void arch_cpu_read_memory_barrier(void);
+static inline void arch_cpu_write_memory_barrier(void);
+static inline void arch_cpu_memory_barrier(void);
+
+/* The common functions map to arch implementation */
+/* Synchronizes all write accesses to memory */
+static inline void cpu_write_memory_barrier(void)
+{
+        return arch_cpu_write_memory_barrier();
+}
+/* Synchronizes all read accesses from memory */
+static inline void cpu_read_memory_barrier(void)
+{
+        return arch_cpu_read_memory_barrier();
+}
+/* Synchronizes all read and write accesses to/from memory */
+static inline void cpu_memory_barrier(void)
+{
+        return arch_cpu_memory_barrier();
+}
+
+/* Prevents compilers from reordering read/write access across this barrier */
+static inline void cpu_compiler_barrier(void)
+{
+        asm volatile ("" : : : "memory");
+}
+#endif /* BARRIER_H */