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hv: Handle holes in GSI i.e. Global System Interrupt for multiple IO-APICs
MADT is used to specify the GSI base for each IO-APIC and the number of interrupt pins per IO-APIC is programmed into Max. Redir. Entry register of that IO-APIC. On platforms with multiple IO-APICs, there can be holes in the GSI space. For example, on a platform with 2 IO-APICs, the following configuration has a hole (from 24 to 31) in the GSI space. IO-APIC 1: GSI base - 0, number of pins - 24 IO-APIC 2: GSI base - 32, number of pins - 8 This patch also adjusts the size for variables used to represent the total number of IO-APICs on the system from uint16_t to uint8_t as the ACPI MADT uses only 8-bits to indicate the unique IO-APIC IDs. Tracked-On: #4151 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
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committed by
wenlingz
parent
85217e362f
commit
f67ac09141
@@ -209,14 +209,14 @@ local_parse_madt(struct acpi_table_madt *madt, uint32_t lapic_id_array[MAX_PCPU_
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return pcpu_num;
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}
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static uint16_t
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static uint8_t
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ioapic_parse_madt(void *madt, struct ioapic_info *ioapic_id_array)
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{
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struct acpi_madt_ioapic *ioapic;
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struct acpi_table_madt *madt_ptr;
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void *first, *end, *iterator;
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struct acpi_subtable_header *entry;
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uint16_t ioapic_idx = 0U;
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uint8_t ioapic_idx = 0U;
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madt_ptr = (struct acpi_table_madt *)madt;
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@@ -261,9 +261,9 @@ uint16_t parse_madt(uint32_t lapic_id_array[MAX_PCPU_NUM])
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return ret;
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}
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uint16_t parse_madt_ioapic(struct ioapic_info *ioapic_id_array)
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uint8_t parse_madt_ioapic(struct ioapic_info *ioapic_id_array)
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{
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uint16_t ret = 0U;
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uint8_t ret = 0U;
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struct acpi_table_rsdp *rsdp = NULL;
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rsdp = get_rsdp();
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@@ -203,7 +203,7 @@ void *get_acpi_tbl(const char *signature);
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struct ioapic_info;
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uint16_t parse_madt(uint32_t lapic_id_array[MAX_PCPU_NUM]);
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uint16_t parse_madt_ioapic(struct ioapic_info *ioapic_id_array);
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uint8_t parse_madt_ioapic(struct ioapic_info *ioapic_id_array);
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#ifdef CONFIG_ACPI_PARSE_ENABLED
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int32_t acpi_fixup(void);
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