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hv: Handle holes in GSI i.e. Global System Interrupt for multiple IO-APICs
MADT is used to specify the GSI base for each IO-APIC and the number of interrupt pins per IO-APIC is programmed into Max. Redir. Entry register of that IO-APIC. On platforms with multiple IO-APICs, there can be holes in the GSI space. For example, on a platform with 2 IO-APICs, the following configuration has a hole (from 24 to 31) in the GSI space. IO-APIC 1: GSI base - 0, number of pins - 24 IO-APIC 2: GSI base - 32, number of pins - 8 This patch also adjusts the size for variables used to represent the total number of IO-APICs on the system from uint16_t to uint8_t as the ACPI MADT uses only 8-bits to indicate the unique IO-APIC IDs. Tracked-On: #4151 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
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committed by
wenlingz
parent
85217e362f
commit
f67ac09141
@@ -21,8 +21,8 @@ struct ioapic_info {
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void ioapic_setup_irqs(void);
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bool ioapic_irq_is_gsi(uint32_t irq);
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uint32_t ioapic_irq_to_pin(uint32_t irq);
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bool is_ioapic_irq(uint32_t irq);
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uint32_t gsi_to_ioapic_pin(uint32_t gsi);
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int32_t init_ioapic_id_info(void);
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uint8_t ioapic_irq_to_ioapic_id(uint32_t irq);
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@@ -88,15 +88,26 @@ void ioapic_gsi_unmask_irq(uint32_t irq);
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void ioapic_get_rte_entry(void *ioapic_base, uint32_t pin, union ioapic_rte *rte);
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/*
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* is_valid is by default false when all the
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* static variables, part of .bss, are initialized to 0s
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* It is set to true, if the corresponding
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* gsi falls in ranges identified by IOAPIC data
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* in ACPI MADT in ioapic_setup_irqs.
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*/
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struct gsi_table {
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uint8_t ioapic_id;
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uint32_t pin;
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void *addr;
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bool is_valid;
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struct {
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uint8_t acpi_id;
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uint8_t index;
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uint32_t pin;
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void *base_addr;
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} ioapic_info;
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};
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void *gsi_to_ioapic_base(uint32_t gsi);
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uint32_t ioapic_get_nr_gsi(void);
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uint32_t get_max_nr_gsi(void);
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uint32_t get_pic_pin_from_ioapic_pin(uint32_t pin_index);
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bool ioapic_is_pin_valid(uint32_t pin);
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bool is_gsi_valid(uint32_t gsi);
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#endif /* IOAPIC_H */
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