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HV: RDT: merge struct rdt_cache and rdt_membw in to a union

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A RDT resource could be CAT or MBA, so only one of struct rdt_cache and struct rdt_membw
would be used at a time. They should be a union.
This commit merge struct rdt_cache and struct rdt_membw in to a union res.

Tracked-On: #4604
Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com
This commit is contained in:
Yan, Like
2020-04-24 09:59:15 +08:00
committed by wenlingz
parent bfe2a1c525
commit f774ee1fba
2 changed files with 20 additions and 22 deletions
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24
hypervisor/include/arch/x86/rdt.h
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@@ -23,21 +23,19 @@ enum {
extern const uint16_t hv_clos;
extern const uint16_t platform_clos_num;
struct rdt_cache {
uint32_t bitmask; /* A bitmask where each set bit indicates the corresponding cache way
may be used by other entities in the platform (e.g. GPU) */
uint16_t cbm_len; /* Length of Cache mask in bits */
};
struct rdt_membw {
uint16_t mba_max; /* Max MBA delay throttling value supported */
bool delay_linear; /* True if memory B/W delay is in linear scale */
};
/* The intel Resource Director Tech(RDT) based Allocation Tech support */
struct rdt_info {
struct rdt_cache cache;
struct rdt_membw membw;
union {
struct {
uint32_t bitmask; /* A bitmask where each set bit indicates the corresponding cache way
may be used by other entities in the platform (e.g. GPU) */
uint16_t cbm_len; /* Length of Cache mask in bits */
} cache;
struct rdt_membw {
uint16_t mba_max; /* Max MBA delay throttling value supported */
bool delay_linear; /* True if memory B/W delay is in linear scale */
} membw;
} res;
uint16_t clos_max; /* Maximum CLOS supported, 0 indicates resource is not supported.*/
uint32_t res_id;
uint32_t msr_base; /* MSR base to program clos mask*/