mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-21 21:19:35 +00:00
hv: refine the function pointer type of port I/O request handlers
In the definition of port i/o handler, struct acrn_vm * pointer is redundant as input, as context of acrn_vm is aleady linked in struct acrn_vcpu * by vcpu->vm, 'vm' is not required as input. this patch removes argument '*vm' from 'io_read_fn_t' & 'io_write_fn_t', use '*vcpu' for them instead. Tracked-On: #861 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
parent
866935a53f
commit
f791574f0e
@ -140,7 +140,7 @@ static inline uint8_t get_slp_typx(uint32_t pm1_cnt)
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return (uint8_t)((pm1_cnt & 0x1fffU) >> BIT_SLP_TYPx);
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return (uint8_t)((pm1_cnt & 0x1fffU) >> BIT_SLP_TYPx);
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}
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}
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static bool pm1ab_io_read(__unused struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t addr, size_t width)
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static bool pm1ab_io_read(struct acrn_vcpu *vcpu, uint16_t addr, size_t width)
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{
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{
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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@ -165,11 +165,16 @@ static inline void enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val, uint32_t
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resume_vm_from_s3(vm, guest_wakeup_vec32); /* jump back to vm */
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resume_vm_from_s3(vm, guest_wakeup_vec32); /* jump back to vm */
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}
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}
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static bool pm1ab_io_write(struct acrn_vm *vm, uint16_t addr, size_t width, uint32_t v)
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/**
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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static bool pm1ab_io_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t width, uint32_t v)
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{
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{
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static uint32_t pm1a_cnt_ready = 0U;
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static uint32_t pm1a_cnt_ready = 0U;
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uint32_t pm1a_cnt_val;
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uint32_t pm1a_cnt_val;
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bool to_write = true;
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bool to_write = true;
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struct acrn_vm *vm = vcpu->vm;
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if (width == 2U) {
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if (width == 2U) {
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uint8_t val = get_slp_typx(v);
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uint8_t val = get_slp_typx(v);
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@ -237,7 +242,7 @@ void register_pm1ab_handler(struct acrn_vm *vm)
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register_gas_io_handler(vm, PM1B_CNT_PIO_IDX, &(sx_data->pm1b_cnt));
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register_gas_io_handler(vm, PM1B_CNT_PIO_IDX, &(sx_data->pm1b_cnt));
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}
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}
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static bool rt_vm_pm1a_io_read(__unused struct acrn_vm *vm, __unused struct acrn_vcpu *vcpu,
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static bool rt_vm_pm1a_io_read(__unused struct acrn_vcpu *vcpu,
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__unused uint16_t addr, __unused size_t width)
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__unused uint16_t addr, __unused size_t width)
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{
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{
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return false;
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return false;
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@ -247,13 +252,17 @@ static bool rt_vm_pm1a_io_read(__unused struct acrn_vm *vm, __unused struct acrn
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* retval true means that we complete the emulation in HV and no need to re-inject the request to DM.
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* retval true means that we complete the emulation in HV and no need to re-inject the request to DM.
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* retval false means that we should re-inject the request to DM.
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* retval false means that we should re-inject the request to DM.
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*/
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*/
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static bool rt_vm_pm1a_io_write(struct acrn_vm *vm, uint16_t addr, size_t width, uint32_t v)
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/**
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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static bool rt_vm_pm1a_io_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t width, uint32_t v)
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{
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{
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if (width != 2U) {
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if (width != 2U) {
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pr_dbg("Invalid address (0x%x) or width (0x%x)", addr, width);
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pr_dbg("Invalid address (0x%x) or width (0x%x)", addr, width);
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} else {
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} else {
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if ((((v & VIRTUAL_PM1A_SLP_EN) != 0U) && (((v & VIRTUAL_PM1A_SLP_TYP) >> 10U) == 5U)) != 0U) {
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if ((((v & VIRTUAL_PM1A_SLP_EN) != 0U) && (((v & VIRTUAL_PM1A_SLP_TYP) >> 10U) == 5U)) != 0U) {
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vm->state = VM_POWERING_OFF;
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vcpu->vm->state = VM_POWERING_OFF;
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}
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}
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}
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}
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@ -110,14 +110,15 @@ static void reset_host(void)
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}
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}
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/**
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/**
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* @pre vcpu != NULL && vm != NULL
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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*/
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static bool handle_reset_reg_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, __unused uint16_t addr,
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static bool handle_reset_reg_read(struct acrn_vcpu *vcpu, __unused uint16_t addr,
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__unused size_t bytes)
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__unused size_t bytes)
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{
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{
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bool ret = true;
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bool ret = true;
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if (is_postlaunched_vm(vm)) {
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if (is_postlaunched_vm(vcpu->vm)) {
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/* re-inject to DM */
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/* re-inject to DM */
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ret = false;
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ret = false;
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} else {
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} else {
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@ -161,12 +162,13 @@ static bool handle_common_reset_reg_write(struct acrn_vm *vm, bool reset)
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}
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}
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/**
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/**
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* @pre vm != NULL
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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*/
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static bool handle_kb_write(struct acrn_vm *vm, __unused uint16_t addr, size_t bytes, uint32_t val)
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static bool handle_kb_write(struct acrn_vcpu *vcpu, __unused uint16_t addr, size_t bytes, uint32_t val)
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{
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{
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/* ignore commands other than system reset */
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/* ignore commands other than system reset */
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return handle_common_reset_reg_write(vm, ((bytes == 1U) && (val == 0xfeU)));
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return handle_common_reset_reg_write(vcpu->vm, ((bytes == 1U) && (val == 0xfeU)));
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}
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}
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/*
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/*
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@ -178,19 +180,25 @@ static bool handle_kb_write(struct acrn_vm *vm, __unused uint16_t addr, size_t b
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* 0: will be dropped if system in S3/S4/S5.
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* 0: will be dropped if system in S3/S4/S5.
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*/
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*/
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/**
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/**
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* @pre vm != NULL
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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*/
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static bool handle_cf9_write(struct acrn_vm *vm, __unused uint16_t addr, size_t bytes, uint32_t val)
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static bool handle_cf9_write(struct acrn_vcpu *vcpu, __unused uint16_t addr, size_t bytes, uint32_t val)
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{
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{
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/* We don't differentiate among hard/soft/warm/cold reset */
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/* We don't differentiate among hard/soft/warm/cold reset */
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return handle_common_reset_reg_write(vm, ((bytes == 1U) && ((val & 0x4U) == 0x4U) && ((val & 0xaU) != 0U)));
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return handle_common_reset_reg_write(vcpu->vm,
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((bytes == 1U) && ((val & 0x4U) == 0x4U) && ((val & 0xaU) != 0U)));
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}
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}
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static bool handle_reset_reg_write(__unused struct acrn_vm *vm, uint16_t addr, size_t bytes, uint32_t val)
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/**
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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static bool handle_reset_reg_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t bytes, uint32_t val)
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{
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{
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if (bytes == 1U) {
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if (bytes == 1U) {
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if (val == host_reset_reg.val) {
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if (val == host_reset_reg.val) {
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if (is_highest_severity_vm(vm)) {
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if (is_highest_severity_vm(vcpu->vm)) {
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reset_host();
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reset_host();
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} else {
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} else {
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/* ignore reset request */
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/* ignore reset request */
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@ -345,8 +345,10 @@ static void dm_emulate_io_complete(struct acrn_vcpu *vcpu)
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/**
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/**
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* @pre width < 8U
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* @pre width < 8U
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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*/
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static bool pio_default_read(__unused struct acrn_vm *vm, struct acrn_vcpu *vcpu,
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static bool pio_default_read(struct acrn_vcpu *vcpu,
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__unused uint16_t addr, size_t width)
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__unused uint16_t addr, size_t width)
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{
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{
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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@ -356,7 +358,12 @@ static bool pio_default_read(__unused struct acrn_vm *vm, struct acrn_vcpu *vcpu
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return true;
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return true;
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}
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}
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static bool pio_default_write(__unused struct acrn_vm *vm, __unused uint16_t addr,
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/**
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* @pre width < 8U
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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static bool pio_default_write(__unused struct acrn_vcpu *vcpu, __unused uint16_t addr,
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__unused size_t width, __unused uint32_t v)
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__unused size_t width, __unused uint32_t v)
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{
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{
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return true; /* ignore write */
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return true; /* ignore write */
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@ -436,11 +443,11 @@ hv_emulate_pio(struct acrn_vcpu *vcpu, struct io_request *io_req)
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}
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}
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if ((pio_req->direction == REQUEST_WRITE) && (io_write != NULL)) {
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if ((pio_req->direction == REQUEST_WRITE) && (io_write != NULL)) {
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if (io_write(vm, port, size, pio_req->value)) {
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if (io_write(vcpu, port, size, pio_req->value)) {
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status = 0;
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status = 0;
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}
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}
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} else if ((pio_req->direction == REQUEST_READ) && (io_read != NULL)) {
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} else if ((pio_req->direction == REQUEST_READ) && (io_read != NULL)) {
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if (io_read(vm, vcpu, port, size)) {
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if (io_read(vcpu, port, size)) {
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status = 0;
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status = 0;
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}
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}
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} else {
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} else {
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@ -52,13 +52,13 @@ static void pci_cfg_clear_cache(struct pci_addr_info *pi)
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}
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}
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/**
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/**
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* @pre vm != NULL
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* @pre vcpu != NULL
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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*/
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static bool pci_cfgaddr_io_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t addr, size_t bytes)
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static bool pci_cfgaddr_io_read(struct acrn_vcpu *vcpu, uint16_t addr, size_t bytes)
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{
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{
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uint32_t val = ~0U;
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uint32_t val = ~0U;
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struct acrn_vpci *vpci = &vm->vpci;
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struct acrn_vpci *vpci = &vcpu->vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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struct pci_addr_info *pi = &vpci->addr_info;
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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@ -77,11 +77,12 @@ static bool pci_cfgaddr_io_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint
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}
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}
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/**
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/**
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* @pre vm != NULL
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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*/
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static bool pci_cfgaddr_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes, uint32_t val)
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static bool pci_cfgaddr_io_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t bytes, uint32_t val)
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{
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{
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struct acrn_vpci *vpci = &vm->vpci;
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struct acrn_vpci *vpci = &vcpu->vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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struct pci_addr_info *pi = &vpci->addr_info;
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if ((addr == (uint16_t)PCI_CONFIG_ADDR) && (bytes == 4U)) {
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if ((addr == (uint16_t)PCI_CONFIG_ADDR) && (bytes == 4U)) {
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@ -109,13 +110,15 @@ static inline bool vpci_is_valid_access(uint32_t offset, uint32_t bytes)
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}
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}
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/**
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/**
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* @pre vm != NULL
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* @pre vcpu != NULL
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* @pre vcpu != NULL
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* @pre vm->vm_id < CONFIG_MAX_VM_NUM
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* @pre vcpu->vm != NULL
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* @pre (get_vm_config(vm->vm_id)->load_order == PRE_LAUNCHED_VM) || (get_vm_config(vm->vm_id)->load_order == SOS_VM)
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* @pre vcpu->vm->vm_id < CONFIG_MAX_VM_NUM
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* @pre (get_vm_config(vcpu->vm->vm_id)->load_order == PRE_LAUNCHED_VM)
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* || (get_vm_config(vcpu->vm->vm_id)->load_order == SOS_VM)
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*/
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*/
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static bool pci_cfgdata_io_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t addr, size_t bytes)
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static bool pci_cfgdata_io_read(struct acrn_vcpu *vcpu, uint16_t addr, size_t bytes)
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{
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{
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struct acrn_vm *vm = vcpu->vm;
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struct acrn_vpci *vpci = &vm->vpci;
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struct acrn_vpci *vpci = &vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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struct pci_addr_info *pi = &vpci->addr_info;
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uint16_t offset = addr - PCI_CONFIG_DATA;
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uint16_t offset = addr - PCI_CONFIG_DATA;
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@ -147,12 +150,15 @@ static bool pci_cfgdata_io_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint
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}
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}
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/**
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/**
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* @pre vm != NULL
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* @pre vcpu != NULL
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* @pre vm->vm_id < CONFIG_MAX_VM_NUM
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* @pre vcpu->vm != NULL
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* @pre (get_vm_config(vm->vm_id)->load_order == PRE_LAUNCHED_VM) || (get_vm_config(vm->vm_id)->load_order == SOS_VM)
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* @pre vcpu->vm->vm_id < CONFIG_MAX_VM_NUM
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* @pre (get_vm_config(vcpu->vm->vm_id)->load_order == PRE_LAUNCHED_VM)
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* || (get_vm_config(vcpu->vm->vm_id)->load_order == SOS_VM)
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*/
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*/
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static bool pci_cfgdata_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes, uint32_t val)
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static bool pci_cfgdata_io_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t bytes, uint32_t val)
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{
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{
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struct acrn_vm *vm = vcpu->vm;
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struct acrn_vpci *vpci = &vm->vpci;
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struct acrn_vpci *vpci = &vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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struct pci_addr_info *pi = &vpci->addr_info;
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uint16_t offset = addr - PCI_CONFIG_DATA;
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uint16_t offset = addr - PCI_CONFIG_DATA;
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@ -718,11 +718,15 @@ static int32_t vpic_master_handler(struct acrn_vpic *vpic, bool in, uint16_t por
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return ret;
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return ret;
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}
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}
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static bool vpic_master_io_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t addr, size_t width)
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/**
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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static bool vpic_master_io_read(struct acrn_vcpu *vcpu, uint16_t addr, size_t width)
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{
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{
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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if (vpic_master_handler(vm_pic(vm), true, addr, width, &pio_req->value) < 0) {
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if (vpic_master_handler(vm_pic(vcpu->vm), true, addr, width, &pio_req->value) < 0) {
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pr_err("pic master read port 0x%x width=%d failed\n",
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pr_err("pic master read port 0x%x width=%d failed\n",
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addr, width);
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addr, width);
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}
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}
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@ -730,12 +734,16 @@ static bool vpic_master_io_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint
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return true;
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return true;
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}
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}
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static bool vpic_master_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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/**
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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static bool vpic_master_io_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t width,
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uint32_t v)
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uint32_t v)
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{
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{
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uint32_t val = v;
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uint32_t val = v;
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if (vpic_master_handler(vm_pic(vm), false, addr, width, &val) < 0) {
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if (vpic_master_handler(vm_pic(vcpu->vm), false, addr, width, &val) < 0) {
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pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
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pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
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__func__, addr, width, val);
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__func__, addr, width, val);
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}
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}
|
||||||
@ -762,23 +770,31 @@ static int32_t vpic_slave_handler(struct acrn_vpic *vpic, bool in, uint16_t port
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vpic_slave_io_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t addr, size_t width)
|
/**
|
||||||
|
* @pre vcpu != NULL
|
||||||
|
* @pre vcpu->vm != NULL
|
||||||
|
*/
|
||||||
|
static bool vpic_slave_io_read(struct acrn_vcpu *vcpu, uint16_t addr, size_t width)
|
||||||
{
|
{
|
||||||
struct pio_request *pio_req = &vcpu->req.reqs.pio;
|
struct pio_request *pio_req = &vcpu->req.reqs.pio;
|
||||||
|
|
||||||
if (vpic_slave_handler(vm_pic(vm), true, addr, width, &pio_req->value) < 0) {
|
if (vpic_slave_handler(vm_pic(vcpu->vm), true, addr, width, &pio_req->value) < 0) {
|
||||||
pr_err("pic slave read port 0x%x width=%d failed\n",
|
pr_err("pic slave read port 0x%x width=%d failed\n",
|
||||||
addr, width);
|
addr, width);
|
||||||
}
|
}
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vpic_slave_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
|
/**
|
||||||
|
* @pre vcpu != NULL
|
||||||
|
* @pre vcpu->vm != NULL
|
||||||
|
*/
|
||||||
|
static bool vpic_slave_io_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t width,
|
||||||
uint32_t v)
|
uint32_t v)
|
||||||
{
|
{
|
||||||
uint32_t val = v;
|
uint32_t val = v;
|
||||||
|
|
||||||
if (vpic_slave_handler(vm_pic(vm), false, addr, width, &val) < 0) {
|
if (vpic_slave_handler(vm_pic(vcpu->vm), false, addr, width, &val) < 0) {
|
||||||
pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
|
pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
|
||||||
__func__, addr, width, val);
|
__func__, addr, width, val);
|
||||||
}
|
}
|
||||||
@ -830,23 +846,31 @@ static int32_t vpic_elc_handler(struct acrn_vpic *vpic, bool in, uint16_t port,
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vpic_elc_io_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t addr, size_t width)
|
/**
|
||||||
|
* @pre vcpu != NULL
|
||||||
|
* @pre vcpu->vm != NULL
|
||||||
|
*/
|
||||||
|
static bool vpic_elc_io_read(struct acrn_vcpu *vcpu, uint16_t addr, size_t width)
|
||||||
{
|
{
|
||||||
struct pio_request *pio_req = &vcpu->req.reqs.pio;
|
struct pio_request *pio_req = &vcpu->req.reqs.pio;
|
||||||
|
|
||||||
if (vpic_elc_handler(vm_pic(vm), true, addr, width, &pio_req->value) < 0) {
|
if (vpic_elc_handler(vm_pic(vcpu->vm), true, addr, width, &pio_req->value) < 0) {
|
||||||
pr_err("pic elc read port 0x%x width=%d failed", addr, width);
|
pr_err("pic elc read port 0x%x width=%d failed", addr, width);
|
||||||
}
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vpic_elc_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
|
/**
|
||||||
|
* @pre vcpu != NULL
|
||||||
|
* @pre vcpu->vm != NULL
|
||||||
|
*/
|
||||||
|
static bool vpic_elc_io_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t width,
|
||||||
uint32_t v)
|
uint32_t v)
|
||||||
{
|
{
|
||||||
uint32_t val = v;
|
uint32_t val = v;
|
||||||
|
|
||||||
if (vpic_elc_handler(vm_pic(vm), false, addr, width, &val) < 0) {
|
if (vpic_elc_handler(vm_pic(vcpu->vm), false, addr, width, &val) < 0) {
|
||||||
pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
|
pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
|
||||||
__func__, addr, width, val);
|
__func__, addr, width, val);
|
||||||
}
|
}
|
||||||
|
@ -44,10 +44,15 @@ static uint8_t cmos_get_reg_val(uint8_t addr)
|
|||||||
return reg;
|
return reg;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vrtc_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t addr, __unused size_t width)
|
/**
|
||||||
|
* @pre vcpu != NULL
|
||||||
|
* @pre vcpu->vm != NULL
|
||||||
|
*/
|
||||||
|
static bool vrtc_read(struct acrn_vcpu *vcpu, uint16_t addr, __unused size_t width)
|
||||||
{
|
{
|
||||||
uint8_t offset;
|
uint8_t offset;
|
||||||
struct pio_request *pio_req = &vcpu->req.reqs.pio;
|
struct pio_request *pio_req = &vcpu->req.reqs.pio;
|
||||||
|
struct acrn_vm *vm = vcpu->vm;
|
||||||
|
|
||||||
offset = vm->vrtc_offset;
|
offset = vm->vrtc_offset;
|
||||||
|
|
||||||
@ -60,11 +65,15 @@ static bool vrtc_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t addr,
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vrtc_write(struct acrn_vm *vm, uint16_t addr, size_t width,
|
/**
|
||||||
|
* @pre vcpu != NULL
|
||||||
|
* @pre vcpu->vm != NULL
|
||||||
|
*/
|
||||||
|
static bool vrtc_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t width,
|
||||||
uint32_t value)
|
uint32_t value)
|
||||||
{
|
{
|
||||||
if ((width == 1U) && (addr == CMOS_ADDR_PORT)) {
|
if ((width == 1U) && (addr == CMOS_ADDR_PORT)) {
|
||||||
vm->vrtc_offset = value & 0x7FU;
|
vcpu->vm->vrtc_offset = (uint8_t)value & 0x7FU;
|
||||||
}
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
|
@ -339,11 +339,15 @@ static void write_reg(struct acrn_vuart *vu, uint16_t reg, uint8_t value_u8)
|
|||||||
vuart_unlock(vu, rflags);
|
vuart_unlock(vu, rflags);
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
|
/**
|
||||||
|
* @pre vcpu != NULL
|
||||||
|
* @pre vcpu->vm != NULL
|
||||||
|
*/
|
||||||
|
static bool vuart_write(struct acrn_vcpu *vcpu, uint16_t offset_arg,
|
||||||
__unused size_t width, uint32_t value)
|
__unused size_t width, uint32_t value)
|
||||||
{
|
{
|
||||||
uint16_t offset = offset_arg;
|
uint16_t offset = offset_arg;
|
||||||
struct acrn_vuart *vu = find_vuart_by_port(vm, offset);
|
struct acrn_vuart *vu = find_vuart_by_port(vcpu->vm, offset);
|
||||||
uint8_t value_u8 = (uint8_t)value;
|
uint8_t value_u8 = (uint8_t)value;
|
||||||
struct acrn_vuart *target_vu = NULL;
|
struct acrn_vuart *target_vu = NULL;
|
||||||
uint64_t rflags;
|
uint64_t rflags;
|
||||||
@ -366,12 +370,15 @@ static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vuart_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t offset_arg,
|
/**
|
||||||
__unused size_t width)
|
* @pre vcpu != NULL
|
||||||
|
* @pre vcpu->vm != NULL
|
||||||
|
*/
|
||||||
|
static bool vuart_read(struct acrn_vcpu *vcpu, uint16_t offset_arg, __unused size_t width)
|
||||||
{
|
{
|
||||||
uint16_t offset = offset_arg;
|
uint16_t offset = offset_arg;
|
||||||
uint8_t iir, reg, intr_reason;
|
uint8_t iir, reg, intr_reason;
|
||||||
struct acrn_vuart *vu = find_vuart_by_port(vm, offset);
|
struct acrn_vuart *vu = find_vuart_by_port(vcpu->vm, offset);
|
||||||
struct pio_request *pio_req = &vcpu->req.reqs.pio;
|
struct pio_request *pio_req = &vcpu->req.reqs.pio;
|
||||||
uint64_t rflags;
|
uint64_t rflags;
|
||||||
|
|
||||||
|
@ -49,10 +49,10 @@ struct acrn_vm;
|
|||||||
struct acrn_vcpu;
|
struct acrn_vcpu;
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
bool (*io_read_fn_t)(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t port, size_t size);
|
bool (*io_read_fn_t)(struct acrn_vcpu *vcpu, uint16_t port, size_t size);
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
bool (*io_write_fn_t)(struct acrn_vm *vm, uint16_t port, size_t size, uint32_t val);
|
bool (*io_write_fn_t)(struct acrn_vcpu *vcpu, uint16_t port, size_t size, uint32_t val);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Describes a single IO handler description entry.
|
* @brief Describes a single IO handler description entry.
|
||||||
|
Loading…
Reference in New Issue
Block a user