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https://github.com/projectacrn/acrn-hypervisor.git
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HV:MM:add 'U/UL' suffix for unsigned contant value
In the current memory module, there are many constatn value without U/UL suffix, it is reported as MISRA C violations by static analysis tool. Add 'U/UL' suffix for unsigned contant value in memory module as needed. Note:In the most case, CPU_PAGE_SIZE(0x1000) is used as unsigned integer contant value, so CPU_PAGE_SIZE is defined as unsigned integer contant value, and it is safety converted into unsigned long type according to MISRA C standard. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@@ -40,7 +40,7 @@
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/* Define page size */
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#define CPU_PAGE_SHIFT 12
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#define CPU_PAGE_SIZE 0x1000
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#define CPU_PAGE_SIZE 0x1000U
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#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000UL
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#define MMU_PTE_PAGE_SHIFT CPU_PAGE_SHIFT
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@@ -331,8 +331,8 @@ enum mem_io_type {
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};
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/* MMIO emulation related structures */
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#define MMIO_TRANS_VALID 1
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#define MMIO_TRANS_INVALID 0
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#define MMIO_TRANS_VALID 1U
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#define MMIO_TRANS_INVALID 0U
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struct mem_io {
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uint64_t paddr; /* Physical address being accessed */
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enum mem_io_type read_write; /* 0 = read / 1 = write operation */
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@@ -8,7 +8,7 @@
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#define MMU_H
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/* Size of all page-table entries (in bytes) */
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#define IA32E_COMM_ENTRY_SIZE 8
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#define IA32E_COMM_ENTRY_SIZE 8U
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/* Definitions common for all IA-32e related paging entries */
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#define IA32E_COMM_P_BIT 0x0000000000000001UL
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@@ -144,8 +144,8 @@
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/* IA32E Paging constants */
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#define IA32E_INDEX_MASK_BITS 9
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#define IA32E_NUM_ENTRIES 512
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#define IA32E_INDEX_MASK (uint64_t)(IA32E_NUM_ENTRIES - 1)
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#define IA32E_NUM_ENTRIES 512U
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#define IA32E_INDEX_MASK (uint64_t)(IA32E_NUM_ENTRIES - 1U)
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#define IA32E_REF_MASK \
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(boot_cpu_data.physical_address_mask)
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#define IA32E_FIRST_BLOCK_INDEX 1
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@@ -210,7 +210,7 @@
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#define MMU_MEM_ATTR_TYPE_MASK \
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(IA32E_PDPTE_PAT_BIT | IA32E_COMM_PCD_BIT | IA32E_COMM_PWT_BIT)
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#define ROUND_PAGE_UP(addr) (((addr) + CPU_PAGE_SIZE - 1U) & CPU_PAGE_MASK)
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#define ROUND_PAGE_UP(addr) (((addr) + (uint64_t)CPU_PAGE_SIZE - 1UL) & CPU_PAGE_MASK)
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#define ROUND_PAGE_DOWN(addr) ((addr) & CPU_PAGE_MASK)
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enum _page_table_type {
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@@ -7,7 +7,7 @@
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#ifndef TRUSTY_H_
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#define TRUSTY_H_
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#define BOOTLOADER_SEED_MAX_ENTRIES 10
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#define BOOTLOADER_SEED_MAX_ENTRIES 10U
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#define RPMB_MAX_PARTITION_NUMBER 6
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#define MMC_PROD_NAME_WITH_PSN_LEN 15
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#define BUP_MKHI_BOOTLOADER_SEED_LEN 64
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@@ -317,10 +317,10 @@
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#define VMX_MIN_NR_VPID 1
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#define VMX_MAX_NR_VPID (1 << 5)
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#define VMX_VPID_TYPE_INDIVIDUAL_ADDR 0
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#define VMX_VPID_TYPE_SINGLE_CONTEXT 1
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#define VMX_VPID_TYPE_ALL_CONTEXT 2
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#define VMX_VPID_TYPE_SINGLE_NON_GLOBAL 3
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#define VMX_VPID_TYPE_INDIVIDUAL_ADDR 0UL
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#define VMX_VPID_TYPE_SINGLE_CONTEXT 1UL
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#define VMX_VPID_TYPE_ALL_CONTEXT 2UL
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#define VMX_VPID_TYPE_SINGLE_NON_GLOBAL 3UL
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#define VMX_VPID_INVVPID (1U << 0) /* (32 - 32) */
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#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1U << 8) /* (40 - 32) */
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@@ -38,7 +38,7 @@
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* NOTE: The required alignment must be a power of 2 (2, 4, 8, 16, 32, etc)
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*/
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#define MEM_ALIGNED_CHECK(value, req_align) \
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(((uint64_t)(value) & ((uint64_t)(req_align) - (uint64_t)1)) == 0)
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(((uint64_t)(value) & ((uint64_t)(req_align) - 1UL)) == 0UL)
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#if !defined(ASSEMBLER) && !defined(LINKER_SCRIPT)
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@@ -31,10 +31,10 @@
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#define REQ_STATE_PROCESSING 2
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#define REQ_STATE_FAILED -1
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#define REQ_PORTIO 0
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#define REQ_MMIO 1
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#define REQ_PCICFG 2
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#define REQ_WP 3
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#define REQ_PORTIO 0U
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#define REQ_MMIO 1U
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#define REQ_PCICFG 2U
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#define REQ_WP 3U
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#define REQUEST_READ 0
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#define REQUEST_WRITE 1
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@@ -106,9 +106,9 @@
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* the parameter for HC_VM_SET_MEMMAP hypercall
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*/
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struct vm_set_memmap {
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#define MAP_MEM 0
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#define MAP_MMIO 1
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#define MAP_UNMAP 2
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#define MAP_MEM 0U
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#define MAP_MMIO 1U
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#define MAP_UNMAP 2U
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/** map type: MAP_MEM, MAP_MMIO or MAP_UNMAP */
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uint32_t type;
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