github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-07-30 06:54:48 +00:00
Code Issues Projects Releases Wiki Activity

hv: fix MISRA-C violations in vpci code: implicit conversion

Browse Source 
458S: Implicit conversion: actual to formal param (MR): "The value of an
actual parameter shall not be implicitly converted to the type of a formal
parameter, if that conversion might result in the loss of information".

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Huihuang Shi <huihuang.shi@intel.com>
This commit is contained in:
Zide Chen 2018-11-06 15:25:47 -08:00 committed by wenlingz
parent d97224a4b5
commit f84f1a216b
5 changed files with 50 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
hypervisor/dm/hw/pci.c
View File

@ -54,18 +54,18 @@ uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
addr = pci_pdev_calc_address(bdf, offset);
/* Write address to ADDRESS register */
pio_write32(addr, PCI_CONFIG_ADDR);
pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
/* Read result from DATA register */
switch (bytes) {
case 1U:
val = (uint32_t)pio_read8(PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
val = (uint32_t)pio_read8((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
break;
case 2U:
val = (uint32_t)pio_read16(PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
val = (uint32_t)pio_read16((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
break;
default:
val = pio_read32(PCI_CONFIG_DATA);
val = pio_read32((uint16_t)PCI_CONFIG_DATA);
break;
}
spinlock_release(&pci_device_lock);
@ -82,18 +82,18 @@ void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint
addr = pci_pdev_calc_address(bdf, offset);
/* Write address to ADDRESS register */
pio_write32(addr, PCI_CONFIG_ADDR);
pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
/* Write value to DATA register */
switch (bytes) {
case 1U:
pio_write8((uint8_t)val, PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
pio_write8((uint8_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
break;
case 2U:
pio_write16((uint16_t)val, PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
pio_write16((uint16_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
break;
default:
pio_write32(val, PCI_CONFIG_DATA);
pio_write32(val, (uint16_t)PCI_CONFIG_DATA);
break;
}
spinlock_release(&pci_device_lock);

4
hypervisor/dm/vpci/core.c
View File

@ -53,10 +53,10 @@ inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t
{
switch (bytes) {
case 1U:
pci_vdev_write_cfg_u8(vdev, offset, val);
pci_vdev_write_cfg_u8(vdev, offset, (uint8_t)val);
break;
case 2U:
pci_vdev_write_cfg_u16(vdev, offset, val);
pci_vdev_write_cfg_u16(vdev, offset, (uint16_t)val);
break;
default:
pci_vdev_write_cfg_u32(vdev, offset, val);

72
hypervisor/dm/vpci/hostbridge.c
View File

@ -40,46 +40,46 @@
static int vdev_hostbridge_init(struct pci_vdev *vdev)
{
/* PCI config space */
pci_vdev_write_cfg_u16(vdev, PCIR_VENDOR, 0x8086U);
pci_vdev_write_cfg_u16(vdev, PCIR_DEVICE, 0x5af0U);
pci_vdev_write_cfg_u16(vdev, PCIR_VENDOR, (uint16_t)0x8086U);
pci_vdev_write_cfg_u16(vdev, PCIR_DEVICE, (uint16_t)0x5af0U);
pci_vdev_write_cfg_u8(vdev, PCIR_REVID, 0xbU);
pci_vdev_write_cfg_u8(vdev, PCIR_REVID, (uint8_t)0xbU);
pci_vdev_write_cfg_u8(vdev, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL
pci_vdev_write_cfg_u8(vdev, PCIR_HDRTYPE, (uint8_t)PCIM_HDRTYPE_NORMAL
| PCIM_MFDEV);
pci_vdev_write_cfg_u8(vdev, PCIR_CLASS, PCIC_BRIDGE);
pci_vdev_write_cfg_u8(vdev, PCIR_SUBCLASS, PCIS_BRIDGE_HOST);
pci_vdev_write_cfg_u8(vdev, PCIR_CLASS, (uint8_t)PCIC_BRIDGE);
pci_vdev_write_cfg_u8(vdev, PCIR_SUBCLASS, (uint8_t)PCIS_BRIDGE_HOST);
pci_vdev_write_cfg_u8(vdev, 0x34U, 0xe0U);
pci_vdev_write_cfg_u8(vdev, 0x3cU, 0xe0U);
pci_vdev_write_cfg_u8(vdev, 0x48U, 0x1U);
pci_vdev_write_cfg_u8(vdev, 0x4aU, 0xd1U);
pci_vdev_write_cfg_u8(vdev, 0x4bU, 0xfeU);
pci_vdev_write_cfg_u8(vdev, 0x50U, 0xc1U);
pci_vdev_write_cfg_u8(vdev, 0x51U, 0x2U);
pci_vdev_write_cfg_u8(vdev, 0x54U, 0x33U);
pci_vdev_write_cfg_u8(vdev, 0x58U, 0x7U);
pci_vdev_write_cfg_u8(vdev, 0x5aU, 0xf0U);
pci_vdev_write_cfg_u8(vdev, 0x5bU, 0x7fU);
pci_vdev_write_cfg_u8(vdev, 0x60U, 0x1U);
pci_vdev_write_cfg_u8(vdev, 0x63U, 0xe0U);
pci_vdev_write_cfg_u8(vdev, 0xabU, 0x80U);
pci_vdev_write_cfg_u8(vdev, 0xacU, 0x2U);
pci_vdev_write_cfg_u8(vdev, 0xb0U, 0x1U);
pci_vdev_write_cfg_u8(vdev, 0xb3U, 0x7cU);
pci_vdev_write_cfg_u8(vdev, 0xb4U, 0x1U);
pci_vdev_write_cfg_u8(vdev, 0xb6U, 0x80U);
pci_vdev_write_cfg_u8(vdev, 0xb7U, 0x7bU);
pci_vdev_write_cfg_u8(vdev, 0xb8U, 0x1U);
pci_vdev_write_cfg_u8(vdev, 0xbbU, 0x7bU);
pci_vdev_write_cfg_u8(vdev, 0xbcU, 0x1U);
pci_vdev_write_cfg_u8(vdev, 0xbfU, 0x80U);
pci_vdev_write_cfg_u8(vdev, 0xe0U, 0x9U);
pci_vdev_write_cfg_u8(vdev, 0xe2U, 0xcU);
pci_vdev_write_cfg_u8(vdev, 0xe3U, 0x1U);
pci_vdev_write_cfg_u8(vdev, 0xf5U, 0xfU);
pci_vdev_write_cfg_u8(vdev, 0xf6U, 0x1cU);
pci_vdev_write_cfg_u8(vdev, 0xf7U, 0x1U);
pci_vdev_write_cfg_u8(vdev, 0x34U, (uint8_t)0xe0U);
pci_vdev_write_cfg_u8(vdev, 0x3cU, (uint8_t)0xe0U);
pci_vdev_write_cfg_u8(vdev, 0x48U, (uint8_t)0x1U);
pci_vdev_write_cfg_u8(vdev, 0x4aU, (uint8_t)0xd1U);
pci_vdev_write_cfg_u8(vdev, 0x4bU, (uint8_t)0xfeU);
pci_vdev_write_cfg_u8(vdev, 0x50U, (uint8_t)0xc1U);
pci_vdev_write_cfg_u8(vdev, 0x51U, (uint8_t)0x2U);
pci_vdev_write_cfg_u8(vdev, 0x54U, (uint8_t)0x33U);
pci_vdev_write_cfg_u8(vdev, 0x58U, (uint8_t)0x7U);
pci_vdev_write_cfg_u8(vdev, 0x5aU, (uint8_t)0xf0U);
pci_vdev_write_cfg_u8(vdev, 0x5bU, (uint8_t)0x7fU);
pci_vdev_write_cfg_u8(vdev, 0x60U, (uint8_t)0x1U);
pci_vdev_write_cfg_u8(vdev, 0x63U, (uint8_t)0xe0U);
pci_vdev_write_cfg_u8(vdev, 0xabU, (uint8_t)0x80U);
pci_vdev_write_cfg_u8(vdev, 0xacU, (uint8_t)0x2U);
pci_vdev_write_cfg_u8(vdev, 0xb0U, (uint8_t)0x1U);
pci_vdev_write_cfg_u8(vdev, 0xb3U, (uint8_t)0x7cU);
pci_vdev_write_cfg_u8(vdev, 0xb4U, (uint8_t)0x1U);
pci_vdev_write_cfg_u8(vdev, 0xb6U, (uint8_t)0x80U);
pci_vdev_write_cfg_u8(vdev, 0xb7U, (uint8_t)0x7bU);
pci_vdev_write_cfg_u8(vdev, 0xb8U, (uint8_t)0x1U);
pci_vdev_write_cfg_u8(vdev, 0xbbU, (uint8_t)0x7bU);
pci_vdev_write_cfg_u8(vdev, 0xbcU, (uint8_t)0x1U);
pci_vdev_write_cfg_u8(vdev, 0xbfU, (uint8_t)0x80U);
pci_vdev_write_cfg_u8(vdev, 0xe0U, (uint8_t)0x9U);
pci_vdev_write_cfg_u8(vdev, 0xe2U, (uint8_t)0xcU);
pci_vdev_write_cfg_u8(vdev, 0xe3U, (uint8_t)0x1U);
pci_vdev_write_cfg_u8(vdev, 0xf5U, (uint8_t)0xfU);
pci_vdev_write_cfg_u8(vdev, 0xf6U, (uint8_t)0x1cU);
pci_vdev_write_cfg_u8(vdev, 0xf7U, (uint8_t)0x1U);
return 0;
}

6
hypervisor/dm/vpci/pci_pt.c
View File

@ -75,10 +75,10 @@ static int vdev_pt_init(struct pci_vdev *vdev)
hva2hpa(vm->arch_vm.nworld_eptp), 48U);
}
ret = assign_iommu_device(vm->iommu, vdev->pdev.bdf.bits.b,
ret = assign_iommu_device(vm->iommu, (uint8_t)vdev->pdev.bdf.bits.b,
(uint8_t)(vdev->pdev.bdf.value & 0xFFU));
pci_command = pci_pdev_read_cfg(vdev->pdev.bdf, PCIR_COMMAND, 2U);
pci_command = (uint16_t)pci_pdev_read_cfg(vdev->pdev.bdf, PCIR_COMMAND, 2U);
/* Disable INTX */
pci_command |= 0x400U;
pci_pdev_write_cfg(vdev->pdev.bdf, PCIR_COMMAND, 2U, pci_command);
@ -91,7 +91,7 @@ static int vdev_pt_deinit(struct pci_vdev *vdev)
int ret;
struct acrn_vm *vm = vdev->vpci->vm;
ret = unassign_iommu_device(vm->iommu, vdev->pdev.bdf.bits.b,
ret = unassign_iommu_device(vm->iommu, (uint8_t)vdev->pdev.bdf.bits.b,
(uint8_t)(vdev->pdev.bdf.value & 0xFFU));
return ret;

2
hypervisor/dm/vpci/vpci.c
View File

@ -136,7 +136,7 @@ void vpci_init(struct acrn_vm *vm)
* register.
*/
if (is_vm0(vm)) {
allow_guest_pio_access(vm, 0xCF9U, 1);
allow_guest_pio_access(vm, (uint16_t)0xCF9U, 1U);
}
}
}