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https://github.com/projectacrn/acrn-hypervisor.git
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HV:treewide:Update exec_vmread/exec_vmwrite and exec_vmread64/exec_vmwrite64
In the hypervisor, VMCS fields include 16-bit fields,
32-bit fields, 64-bit fields and natural-width fields.
In the current implement, there are exec_vmread/exec_vmwrite
used for accessing 32-bit fields, 64-bit field and
natural-width fields. This usage will confue developer.
So there are many type casting for the return value and
parameters vmread/vmwrite operations.
Since exec_vmread/exec_vmwrite and exec_vmread64/exec_vmwrite64
are the same, update current exec_vmread/exec_vmwrite
implement into exec_vmread64/exec_vmwrite64 implement
and add MACRO define for exec_vmread/exec_vmwrite in
head file;
To access 64-bit fields in VMCS, callers use
exec_vmread64/exec_vmwrite64;
Update related variables type for vmread/vmwrite operations;
Update related caller according to VMCS fields size.
Note:Natural-width fields have 64 bits on processors
that support Intel 64 architecture.To access natural-width
fields in VMCS, callers still use exec_vmread/exec_vmwrite,
keep the current implementation.
V1--V2:
This is new part of this patch serial to only
update 64-bit vmread/vmread opertions and related
caller, for netural width fields, still use exec_vmread
or exec_vmwrite.
V2-->V3:
Fix few mistake updations for netural fields in VMCS,
just keep exec_vmread/exec_vmwrite to access them;
Fix few mistake updations for 64-bit fields in VMCS.
V3--V4:
Add "016ll" for 64-bit variable in log function;
Few updates for coding style;
Rename lssd32_idx as tr_sel in VMX module.
V4-->V5:
Use CPU_NATURAL_LAST in the vm_get_register and
vm_set_register to make condition statement more
understandable.
Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Xiangyang Wu
lijinxia
parent
612cdceaca
commit
f912953539
@ -471,7 +471,7 @@ int ept_misconfig_vmexit_handler(__unused struct vcpu *vcpu)
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/* TODO - EPT Violation handler */
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pr_info("%s, Guest linear address: 0x%016llx ",
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__func__, exec_vmread64(VMX_GUEST_LINEAR_ADDR));
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__func__, exec_vmread(VMX_GUEST_LINEAR_ADDR));
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pr_info("%s, Guest physical address: 0x%016llx ",
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__func__, exec_vmread64(VMX_GUEST_PHYSICAL_ADDR_FULL));
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@ -44,8 +44,10 @@ int vm_get_register(struct vcpu *vcpu, enum cpu_reg_name reg, uint64_t *retval)
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uint32_t field = get_vmcs_field(reg);
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if (field != VMX_INVALID_VMCS_FIELD) {
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if (reg < CPU_REG_64BIT_LAST) {
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if (reg < CPU_REG_NATURAL_LAST) {
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*retval = exec_vmread(field);
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} else if (reg < CPU_REG_64BIT_LAST) {
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*retval = exec_vmread64(field);
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} else {
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*retval = (uint64_t)exec_vmread16(field);
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}
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@ -77,8 +79,10 @@ int vm_set_register(struct vcpu *vcpu, enum cpu_reg_name reg, uint64_t val)
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uint32_t field = get_vmcs_field(reg);
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if (field != VMX_INVALID_VMCS_FIELD) {
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if (reg < CPU_REG_64BIT_LAST) {
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if (reg < CPU_REG_NATURAL_LAST) {
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exec_vmwrite(field, val);
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} else if (reg <= CPU_REG_64BIT_LAST) {
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exec_vmwrite64(field, val);
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} else {
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exec_vmwrite16(field, (uint16_t)val);
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}
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@ -193,8 +193,8 @@ int start_vcpu(struct vcpu *vcpu)
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*/
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instlen = vcpu->arch_vcpu.inst_len;
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rip = cur_context->rip;
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exec_vmwrite(VMX_GUEST_RIP, ((rip + instlen) &
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0xFFFFFFFFFFFFFFFF));
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exec_vmwrite(VMX_GUEST_RIP, ((rip +(uint64_t)instlen) &
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0xFFFFFFFFFFFFFFFFUL));
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/* Resume the VM */
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status = vmx_vmrun(cur_context, VM_RESUME, ibrs_type);
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@ -2221,14 +2221,14 @@ apicv_set_tmr(__unused struct vlapic *vlapic, uint32_t vector, bool level)
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mask = 1UL << (vector % 64U);
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field = VMX_EOI_EXIT(vector);
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val = exec_vmread(field);
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val = exec_vmread64(field);
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if (level) {
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val |= mask;
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} else {
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val &= ~mask;
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}
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exec_vmwrite(field, val);
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exec_vmwrite64(field, val);
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}
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/* Update the VMX_EOI_EXIT according to related tmr */
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@ -232,7 +232,7 @@ static void save_world_ctx(struct run_context *context)
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* the wrmsr handler keeps track of 'ia32_pat', and we only
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* need to load 'vmx_ia32_pat' here.
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*/
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context->vmx_ia32_pat = exec_vmread(VMX_GUEST_IA32_PAT_FULL);
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context->vmx_ia32_pat = exec_vmread64(VMX_GUEST_IA32_PAT_FULL);
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context->ia32_efer = exec_vmread64(VMX_GUEST_IA32_EFER_FULL);
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context->ia32_sysenter_esp = exec_vmread(VMX_GUEST_IA32_SYSENTER_ESP);
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context->ia32_sysenter_eip = exec_vmread(VMX_GUEST_IA32_SYSENTER_EIP);
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@ -426,7 +426,7 @@ static bool init_secure_world_env(struct vcpu *vcpu,
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exec_vmwrite(VMX_GUEST_RSP,
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TRUSTY_EPT_REBASE_GPA + size);
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exec_vmwrite(VMX_TSC_OFFSET_FULL,
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exec_vmwrite64(VMX_TSC_OFFSET_FULL,
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vcpu->arch_vcpu.contexts[SECURE_WORLD].tsc_offset);
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return setup_trusty_info(vcpu, size, base_hpa);
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@ -195,31 +195,19 @@ int exec_vmptrld(void *addr)
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return status;
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}
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uint64_t exec_vmread(uint32_t field)
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uint64_t exec_vmread64(uint32_t field_full)
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{
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uint64_t value;
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asm volatile (
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"vmread %%rdx, %%rax "
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: "=a" (value)
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: "d"(field)
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: "d"(field_full)
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: "cc");
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return value;
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}
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uint64_t exec_vmread64(uint32_t field_full)
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{
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uint64_t low;
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low = exec_vmread(field_full);
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#ifdef __i386__
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low += exec_vmread(field_full + 1) << 32;
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#endif
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return low;
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}
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uint32_t exec_vmread32(uint32_t field)
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{
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uint64_t value;
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@ -238,27 +226,14 @@ uint16_t exec_vmread16(uint32_t field)
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return (uint16_t)value;
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}
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void exec_vmwrite(uint32_t field, uint64_t value)
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void exec_vmwrite64(uint32_t field_full, uint64_t value)
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{
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asm volatile (
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"vmwrite %%rax, %%rdx "
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: : "a" (value), "d"(field)
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: : "a" (value), "d"(field_full)
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: "cc");
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}
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void exec_vmwrite64(unsigned int field_full, uint64_t value)
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{
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#ifdef __i386__
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int low = (int)(value & 0xFFFFFFFF);
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int high = (int)((value >> 32) & 0xFFFFFFFF);
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exec_vmwrite(field_full, low);
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exec_vmwrite(field_full + 1, high);
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#else
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exec_vmwrite(field_full, value);
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#endif
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}
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void exec_vmwrite32(uint32_t field, uint32_t value)
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{
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exec_vmwrite64(field, (uint64_t)value);
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@ -363,8 +338,8 @@ int vmx_wrmsr_pat(struct vcpu *vcpu, uint64_t value)
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* If context->cr0.CD is set, we defer any further requests to write
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* guest's IA32_PAT, until the time when guest's CR0.CD is being cleared
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*/
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if ((context->cr0 & CR0_CD) == 0U) {
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exec_vmwrite(VMX_GUEST_IA32_PAT_FULL, value);
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if ((context->cr0 & CR0_CD) == 0UL) {
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, value);
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}
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return 0;
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}
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@ -451,11 +426,11 @@ int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0)
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* IA32_PAT with all-UC entries to emulate the cache
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* disabled behavior
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*/
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exec_vmwrite(VMX_GUEST_IA32_PAT_FULL, PAT_ALL_UC_VALUE);
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, PAT_ALL_UC_VALUE);
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CACHE_FLUSH_INVALIDATE_ALL();
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} else {
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/* Restore IA32_PAT to enable cache again */
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exec_vmwrite(VMX_GUEST_IA32_PAT_FULL, context->ia32_pat);
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, context->ia32_pat);
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}
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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@ -566,10 +541,11 @@ static void init_guest_state(struct vcpu *vcpu)
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uint32_t value32;
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uint64_t value64;
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uint16_t sel;
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uint32_t limit, access, base;
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uint32_t ldt_idx = 0x38;
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int es = 0, ss = 0, ds = 0, fs = 0, gs = 0, data32_idx;
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uint32_t lssd32_idx = 0x70;
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uint32_t limit, access;
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uint64_t base;
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uint16_t ldt_idx = 0x38U;
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uint16_t es = 0U, ss = 0U, ds = 0U, fs = 0U, gs = 0U, data32_idx;
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uint16_t tr_sel = 0x70U;
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struct vm *vm = vcpu->vm;
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struct run_context *cur_context =
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&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context];
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@ -615,7 +591,7 @@ static void init_guest_state(struct vcpu *vcpu)
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/* Set up Flags - the value of RFLAGS on VM entry */
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/***************************************************/
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field = VMX_GUEST_RFLAGS;
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cur_context->rflags = 0x2; /* Bit 1 is a active high reserved bit */
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cur_context->rflags = 0x2UL; /* Bit 1 is a active high reserved bit */
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exec_vmwrite(field, cur_context->rflags);
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pr_dbg("VMX_GUEST_RFLAGS: 0x%016llx ", cur_context->rflags);
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@ -698,31 +674,31 @@ static void init_guest_state(struct vcpu *vcpu)
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/***************************************************/
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/* Set up guest instruction pointer */
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field = VMX_GUEST_RIP;
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value32 = 0U;
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value64 = 0UL;
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if (vcpu_mode == CPU_MODE_REAL) {
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/* RIP is set here */
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if (is_vcpu_bsp(vcpu)) {
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if ((uint64_t)vcpu->entry_addr < 0x100000UL) {
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value32 = (uint64_t)vcpu->entry_addr & 0x0FUL;
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value64 = (uint64_t)vcpu->entry_addr & 0x0FUL;
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}
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else {
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value32 = 0x0000FFF0U;
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value64 = 0x0000FFF0UL;
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}
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}
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} else {
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value32 = (uint32_t)((uint64_t)vcpu->entry_addr);
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value64 = (uint64_t)vcpu->entry_addr;
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}
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pr_dbg("GUEST RIP on VMEntry %x ", value32);
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exec_vmwrite(field, value32);
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pr_dbg("GUEST RIP on VMEntry %016llx ", value64);
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exec_vmwrite(field, value64);
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if (vcpu_mode == CPU_MODE_64BIT) {
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/* Set up guest stack pointer to 0 */
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field = VMX_GUEST_RSP;
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value32 = 0U;
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pr_dbg("GUEST RSP on VMEntry %x ",
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value32);
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exec_vmwrite(field, value32);
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value64 = 0UL;
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pr_dbg("GUEST RSP on VMEntry %016llx ",
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value64);
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exec_vmwrite(field, value64);
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}
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/***************************************************/
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@ -806,9 +782,9 @@ static void init_guest_state(struct vcpu *vcpu)
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/***************************************************/
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/* Set up guest Debug register */
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field = VMX_GUEST_DR7;
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value = 0x400;
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exec_vmwrite(field, value);
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pr_dbg("VMX_GUEST_DR7: 0x%016llx ", value);
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value64 = 0x400UL;
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_DR7: 0x%016llx ", value64);
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/***************************************************/
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/* ES, CS, SS, DS, FS, GS */
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@ -903,26 +879,26 @@ static void init_guest_state(struct vcpu *vcpu)
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/* Base */
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if (vcpu_mode == CPU_MODE_REAL) {
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value = es << 4;
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value64 = (uint64_t)es << 4U;
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} else {
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value = 0UL;
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value64 = 0UL;
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}
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field = VMX_GUEST_ES_BASE;
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exec_vmwrite(field, value);
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pr_dbg("VMX_GUEST_ES_BASE: 0x%016llx ", value);
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_ES_BASE: 0x%016llx ", value64);
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field = VMX_GUEST_SS_BASE;
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exec_vmwrite(field, value);
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pr_dbg("VMX_GUEST_SS_BASE: 0x%016llx ", value);
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_SS_BASE: 0x%016llx ", value64);
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field = VMX_GUEST_DS_BASE;
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exec_vmwrite(field, value);
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pr_dbg("VMX_GUEST_DS_BASE: 0x%016llx ", value);
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_DS_BASE: 0x%016llx ", value64);
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field = VMX_GUEST_FS_BASE;
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exec_vmwrite(field, value);
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pr_dbg("VMX_GUEST_FS_BASE: 0x%016llx ", value);
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_FS_BASE: 0x%016llx ", value64);
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field = VMX_GUEST_GS_BASE;
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exec_vmwrite(field, value);
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pr_dbg("VMX_GUEST_GS_BASE: 0x%016llx ", value);
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_GS_BASE: 0x%016llx ", value64);
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/***************************************************/
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/* LDT and TR (dummy) */
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@ -943,13 +919,13 @@ static void init_guest_state(struct vcpu *vcpu)
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pr_dbg("VMX_GUEST_LDTR_ATTR: 0x%x ", value32);
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field = VMX_GUEST_LDTR_BASE;
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value32 = 0x00U;
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exec_vmwrite(field, value32);
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pr_dbg("VMX_GUEST_LDTR_BASE: 0x%x ", value32);
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value64 = 0x00UL;
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_LDTR_BASE: 0x%016llx ", value64);
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/* Task Register */
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field = VMX_GUEST_TR_SEL;
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value16 = lssd32_idx;
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value16 = tr_sel;
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exec_vmwrite16(field, value16);
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pr_dbg("VMX_GUEST_TR_SEL: 0x%hu ", value16);
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@ -964,9 +940,9 @@ static void init_guest_state(struct vcpu *vcpu)
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pr_dbg("VMX_GUEST_TR_ATTR: 0x%x ", value32);
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field = VMX_GUEST_TR_BASE;
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value32 = 0x00U;
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exec_vmwrite(field, value32);
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pr_dbg("VMX_GUEST_TR_BASE: 0x%x ", value32);
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value64 = 0x00UL;
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_TR_BASE: 0x%016llx ", value64);
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field = VMX_GUEST_INTERRUPTIBILITY_INFO;
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value32 = 0U;
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@ -1004,24 +980,24 @@ static void init_guest_state(struct vcpu *vcpu)
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/* Set up guest pending debug exception */
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field = VMX_GUEST_PENDING_DEBUG_EXCEPT;
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value = 0x0UL;
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exec_vmwrite(field, value);
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pr_dbg("VMX_GUEST_PENDING_DEBUG_EXCEPT: 0x%016llx ", value);
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value64 = 0x0UL;
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_PENDING_DEBUG_EXCEPT: 0x%016llx ", value64);
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/* These fields manage host and guest system calls * pg 3069 31.10.4.2
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* - set up these fields with * contents of current SYSENTER ESP and
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* EIP MSR values
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*/
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field = VMX_GUEST_IA32_SYSENTER_ESP;
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value = msr_read(MSR_IA32_SYSENTER_ESP);
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exec_vmwrite(field, value);
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value64 = msr_read(MSR_IA32_SYSENTER_ESP);
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_IA32_SYSENTER_ESP: 0x%016llx ",
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value);
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value64);
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field = VMX_GUEST_IA32_SYSENTER_EIP;
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value = msr_read(MSR_IA32_SYSENTER_EIP);
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exec_vmwrite(field, value);
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value64 = msr_read(MSR_IA32_SYSENTER_EIP);
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exec_vmwrite(field, value64);
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pr_dbg("VMX_GUEST_IA32_SYSENTER_EIP: 0x%016llx ",
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value);
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value64);
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}
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static void init_host_state(__unused struct vcpu *vcpu)
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@ -1198,9 +1174,9 @@ static void init_host_state(__unused struct vcpu *vcpu)
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/* Set up host instruction pointer on VM Exit */
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field = VMX_HOST_RIP;
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value64 = (uint64_t)&vm_exit;
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pr_dbg("HOST RIP on VMExit %x ", value32);
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pr_dbg("HOST RIP on VMExit %016llx ", value64);
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exec_vmwrite(field, value64);
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pr_dbg("vm exit return address = %x ", value32);
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pr_dbg("vm exit return address = %016llx ", value64);
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/* These fields manage host and guest system calls * pg 3069 31.10.4.2
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* - set up these fields with * contents of current SYSENTER ESP and
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@ -1231,7 +1207,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
|
||||
/* Set up VM Execution control to enable Set VM-exits on external
|
||||
* interrupts preemption timer - pg 2899 24.6.1
|
||||
*/
|
||||
value32 = msr_read(MSR_IA32_VMX_PINBASED_CTLS);
|
||||
value32 = (uint32_t)msr_read(MSR_IA32_VMX_PINBASED_CTLS);
|
||||
|
||||
|
||||
/* enable external interrupt VM Exit */
|
||||
@ -1318,7 +1294,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
|
||||
}
|
||||
|
||||
if (cpu_has_cap(X86_FEATURE_OSXSAVE)) {
|
||||
exec_vmwrite64(VMX_XSS_EXITING_BITMAP_FULL, 0);
|
||||
exec_vmwrite64(VMX_XSS_EXITING_BITMAP_FULL, 0UL);
|
||||
value32 |= VMX_PROCBASED_CTLS2_XSVE_XRSTR;
|
||||
}
|
||||
|
||||
@ -1360,7 +1336,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
|
||||
* TODO: introduce API to make this data driven based
|
||||
* on VMX_EPT_VPID_CAP
|
||||
*/
|
||||
value64 = vm->arch_vm.nworld_eptp | (3UL << 3) | 6UL;
|
||||
value64 = vm->arch_vm.nworld_eptp | (3UL << 3U) | 6UL;
|
||||
exec_vmwrite64(VMX_EPT_POINTER_FULL, value64);
|
||||
pr_dbg("VMX_EPT_POINTER: 0x%016llx ", value64);
|
||||
|
||||
@ -1401,13 +1377,13 @@ static void init_exec_ctrl(struct vcpu *vcpu)
|
||||
init_msr_emulation(vcpu);
|
||||
|
||||
/* Set up executive VMCS pointer - pg 2905 24.6.10 */
|
||||
exec_vmwrite64(VMX_EXECUTIVE_VMCS_PTR_FULL, 0);
|
||||
exec_vmwrite64(VMX_EXECUTIVE_VMCS_PTR_FULL, 0UL);
|
||||
|
||||
/* Setup Time stamp counter offset - pg 2902 24.6.5 */
|
||||
exec_vmwrite64(VMX_TSC_OFFSET_FULL, 0);
|
||||
exec_vmwrite64(VMX_TSC_OFFSET_FULL, 0UL);
|
||||
|
||||
/* Set up the link pointer */
|
||||
exec_vmwrite64(VMX_VMS_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
|
||||
exec_vmwrite64(VMX_VMS_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFUL);
|
||||
|
||||
/* Natural-width */
|
||||
pr_dbg("Natural-width*********");
|
||||
@ -1419,10 +1395,10 @@ static void init_exec_ctrl(struct vcpu *vcpu)
|
||||
* if operand does not match one of these register values a VM exit
|
||||
* would occur
|
||||
*/
|
||||
exec_vmwrite(VMX_CR3_TARGET_0, 0);
|
||||
exec_vmwrite(VMX_CR3_TARGET_1, 0);
|
||||
exec_vmwrite(VMX_CR3_TARGET_2, 0);
|
||||
exec_vmwrite(VMX_CR3_TARGET_3, 0);
|
||||
exec_vmwrite(VMX_CR3_TARGET_0, 0UL);
|
||||
exec_vmwrite(VMX_CR3_TARGET_1, 0UL);
|
||||
exec_vmwrite(VMX_CR3_TARGET_2, 0UL);
|
||||
exec_vmwrite(VMX_CR3_TARGET_3, 0UL);
|
||||
}
|
||||
|
||||
static void init_entry_ctrl(__unused struct vcpu *vcpu)
|
||||
@ -1549,15 +1525,15 @@ static void override_uefi_vmcs(struct vcpu *vcpu)
|
||||
|
||||
/* Base */
|
||||
field = VMX_GUEST_ES_BASE;
|
||||
exec_vmwrite(field, efi_ctx->es_sel << 4);
|
||||
exec_vmwrite(field, efi_ctx->es_sel << 4U);
|
||||
field = VMX_GUEST_SS_BASE;
|
||||
exec_vmwrite(field, efi_ctx->ss_sel << 4);
|
||||
exec_vmwrite(field, efi_ctx->ss_sel << 4U);
|
||||
field = VMX_GUEST_DS_BASE;
|
||||
exec_vmwrite(field, efi_ctx->ds_sel << 4);
|
||||
exec_vmwrite(field, efi_ctx->ds_sel << 4U);
|
||||
field = VMX_GUEST_FS_BASE;
|
||||
exec_vmwrite(field, efi_ctx->fs_sel << 4);
|
||||
exec_vmwrite(field, efi_ctx->fs_sel << 4U);
|
||||
field = VMX_GUEST_GS_BASE;
|
||||
exec_vmwrite(field, efi_ctx->gs_sel << 4);
|
||||
exec_vmwrite(field, efi_ctx->gs_sel << 4U);
|
||||
|
||||
/* RSP */
|
||||
field = VMX_GUEST_RSP;
|
||||
@ -1566,8 +1542,8 @@ static void override_uefi_vmcs(struct vcpu *vcpu)
|
||||
|
||||
/* GDTR Base */
|
||||
field = VMX_GUEST_GDTR_BASE;
|
||||
exec_vmwrite(field, (uint64_t)efi_ctx->gdt.base);
|
||||
pr_dbg("VMX_GUEST_GDTR_BASE: 0x%x ", efi_ctx->gdt.base);
|
||||
exec_vmwrite(field, efi_ctx->gdt.base);
|
||||
pr_dbg("VMX_GUEST_GDTR_BASE: 0x%016llx ", efi_ctx->gdt.base);
|
||||
|
||||
/* GDTR Limit */
|
||||
field = VMX_GUEST_GDTR_LIMIT;
|
||||
@ -1576,8 +1552,8 @@ static void override_uefi_vmcs(struct vcpu *vcpu)
|
||||
|
||||
/* IDTR Base */
|
||||
field = VMX_GUEST_IDTR_BASE;
|
||||
exec_vmwrite(field, (uint64_t)efi_ctx->idt.base);
|
||||
pr_dbg("VMX_GUEST_IDTR_BASE: 0x%x ", efi_ctx->idt.base);
|
||||
exec_vmwrite(field, efi_ctx->idt.base);
|
||||
pr_dbg("VMX_GUEST_IDTR_BASE: 0x%016llx ", efi_ctx->idt.base);
|
||||
|
||||
/* IDTR Limit */
|
||||
field = VMX_GUEST_IDTR_LIMIT;
|
||||
@ -1588,7 +1564,7 @@ static void override_uefi_vmcs(struct vcpu *vcpu)
|
||||
/* Interrupt */
|
||||
field = VMX_GUEST_RFLAGS;
|
||||
/* clear flags for CF/PF/AF/ZF/SF/OF */
|
||||
cur_context->rflags = efi_ctx->rflags & ~(0x8d5);
|
||||
cur_context->rflags = efi_ctx->rflags & ~(0x8d5UL);
|
||||
exec_vmwrite(field, cur_context->rflags);
|
||||
pr_dbg("VMX_GUEST_RFLAGS: 0x%016llx ", cur_context->rflags);
|
||||
}
|
||||
|
||||
@ -412,15 +412,16 @@ int exec_vmxon_instr(uint16_t pcpu_id);
|
||||
* @return the lower 32-bit outside IA-32e mode for 64-bit fields.
|
||||
* @return full contents for 32-bit fields, with higher 32-bit set to 0.
|
||||
*/
|
||||
uint64_t exec_vmread(uint32_t field);
|
||||
|
||||
uint16_t exec_vmread16(uint32_t field);
|
||||
uint32_t exec_vmread32(uint32_t field);
|
||||
uint64_t exec_vmread64(uint32_t field_full);
|
||||
void exec_vmwrite(uint32_t field, uint64_t value);
|
||||
#define exec_vmread exec_vmread64
|
||||
|
||||
void exec_vmwrite16(uint32_t field, uint16_t value);
|
||||
void exec_vmwrite32(uint32_t field, uint32_t value);
|
||||
void exec_vmwrite64(uint32_t field_full, uint64_t value);
|
||||
#define exec_vmwrite exec_vmwrite64
|
||||
|
||||
int init_vmcs(struct vcpu *vcpu);
|
||||
|
||||
int vmx_off(uint16_t pcpu_id);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user