From fad6a94030d9ae0c3219506f79b92dbc2bda256b Mon Sep 17 00:00:00 2001
From: Jian Jun Chen <jian.jun.chen@intel.com>
Date: Fri, 29 Jan 2021 11:31:35 +0800
Subject: [PATCH] dm: align bar base addr to PAGE_SIZE at least

PCI spec said that BAR base should be naturally aligned. But on
ACRN if the bar size < PAGE_SIZE, BAR base should be aligned with
PAGE_SIZE. This is because the minimal size that EPT can map/unmap
is PAGE_SIZE.

Tracked-On: #5717
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
---
 devicemodel/hw/pci/core.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c
index 4f15bf6c8..3dcad83c9 100644
--- a/devicemodel/hw/pci/core.c
+++ b/devicemodel/hw/pci/core.c
@@ -26,6 +26,7 @@
  * $FreeBSD$
  */
 
+#include <sys/user.h>
 #include <errno.h>
 #include <pthread.h>
 #include <stdio.h>
@@ -564,6 +565,13 @@ pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
 		return -1;
 	}
 
+	/* PCI spec said that BAR base should be naturally aligned. On ACRN
+	 * if the bar size < PAGE_SIZE, BAR base should be aligned with
+	 * PAGE_SIZE. This is because the minimal size that EPT can map/unmap
+	 * is PAGE_SIZE.
+	 */
+	if (size < PAGE_SIZE)
+		size = PAGE_SIZE;
 	base = roundup2(*baseptr, size);
 
 	/* TODO:Currently, we only reserve gvt mmio regions,