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hv: Support Queued Invalidation

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As we enable Interrupt Remapping Hardware in ACRN, Queued Invalidation
(QI) needs to be used clear DMAR hardware caches. This patch introduces
Queued Invalidation APIs. Code related to Register based Invalidation
is removed from ACRN and platforms that do not support QI cannot boot
with ACRN after this patch.

Tracked-On: #2426
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
This commit is contained in:
Grandhi, Sainath
2019-01-26 00:04:46 -08:00
committed by Eddie Dong
parent 80dc0bce3e
commit fb6e9267f3
2 changed files with 131 additions and 39 deletions
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23
hypervisor/include/arch/x86/vtd.h
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@@ -284,9 +284,12 @@ static inline uint8_t iommu_ecap_pds(uint64_t ecap)
#define DMA_CCMD_GLOBAL_INVL (1UL << 61U)
#define DMA_CCMD_DOMAIN_INVL (2UL << 61U)
#define DMA_CCMD_DEVICE_INVL (3UL << 61U)
#define DMA_CONTEXT_GLOBAL_INVL (1UL << 4U)
#define DMA_CONTEXT_DOMAIN_INVL (2UL << 4U)
#define DMA_CONTEXT_DEVICE_INVL (3UL << 4U)
static inline uint64_t dma_ccmd_fm(uint8_t fm)
{
return (((uint64_t)fm & 0x3UL) << 32UL);
return (((uint64_t)fm & 0x3UL) << 48UL);
}
#define DMA_CCMD_MASK_NOBIT 0UL
@@ -295,12 +298,12 @@ static inline uint64_t dma_ccmd_fm(uint8_t fm)
#define DMA_CCMD_MASK_3BIT 3UL
static inline uint64_t dma_ccmd_sid(uint16_t sid)
{
return (((uint64_t)sid & 0xffffUL) << 16UL);
return (((uint64_t)sid & 0xffffUL) << 32UL);
}
static inline uint16_t dma_ccmd_did(uint16_t did)
static inline uint64_t dma_ccmd_did(uint16_t did)
{
return (did & 0xffffU);
return (((uint64_t)did & 0xffffUL) << 16UL);
}
static inline uint8_t dma_ccmd_get_caig_32(uint32_t gaig)
@@ -312,14 +315,14 @@ static inline uint8_t dma_ccmd_get_caig_32(uint32_t gaig)
/* IOTLB_REG */
#define DMA_IOTLB_IVT (((uint64_t)1UL) << 63U)
#define DMA_IOTLB_IVT_32 (((uint32_t)1U) << 31U)
#define DMA_IOTLB_GLOBAL_INVL (((uint64_t)1UL) << 60U)
#define DMA_IOTLB_DOMAIN_INVL (((uint64_t)2UL) << 60U)
#define DMA_IOTLB_PAGE_INVL (((uint64_t)3UL) << 60U)
#define DMA_IOTLB_DR (((uint64_t)1UL) << 49U)
#define DMA_IOTLB_DW (((uint64_t)1UL) << 48U)
#define DMA_IOTLB_GLOBAL_INVL (((uint64_t)1UL) << 4U)
#define DMA_IOTLB_DOMAIN_INVL (((uint64_t)2UL) << 4U)
#define DMA_IOTLB_PAGE_INVL (((uint64_t)3UL) << 4U)
#define DMA_IOTLB_DR (((uint64_t)1UL) << 7U)
#define DMA_IOTLB_DW (((uint64_t)1UL) << 6U)
static inline uint64_t dma_iotlb_did(uint16_t did)
{
return (((uint64_t)did & 0xffffUL) << 32UL);
return (((uint64_t)did & 0xffffUL) << 16UL);
}
static inline uint8_t dma_iotlb_get_iaig_32(uint32_t iai)