mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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HV: move vioapic.c & vpic.c to 'dm' folder
- 'hypervisor/dm' holds devices emulation source in hypervisor Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang
Jack Ren
@@ -1,663 +0,0 @@
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/*-
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* Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define pr_prefix "vioapic: "
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#include <hypervisor.h>
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#define REDIR_ENTRIES_HW 120U /* SOS align with native ioapic */
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#define RTBL_RO_BITS (uint32_t)(IOAPIC_RTE_REM_IRR | IOAPIC_RTE_DELIVS)
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#define NEED_TMR_UPDATE (~(IOAPIC_RTE_INTMASK | IOAPIC_RTE_INTPOL))
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#define ACRN_DBG_IOAPIC 6U
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#define ACRN_IOAPIC_VERSION 0x11U
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struct vioapic {
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struct vm *vm;
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spinlock_t mtx;
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uint32_t id;
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uint32_t ioregsel;
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union ioapic_rte rtbl[REDIR_ENTRIES_HW];
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/* sum of pin asserts (+1) and deasserts (-1) */
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int32_t acnt[REDIR_ENTRIES_HW];
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};
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#define VIOAPIC_LOCK(vioapic) spinlock_obtain(&((vioapic)->mtx))
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#define VIOAPIC_UNLOCK(vioapic) spinlock_release(&((vioapic)->mtx))
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#define IOAPIC_ID_MASK 0x0f000000U
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#define MASK_ALL_INTERRUPTS 0x0001000000010000UL
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#define IOAPIC_RTE_LOW_INTVEC ((uint32_t)IOAPIC_RTE_INTVEC)
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static inline const char *pinstate_str(bool asserted)
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{
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return (asserted) ? "asserted" : "deasserted";
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}
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static struct vioapic *
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vm_ioapic(struct vm *vm)
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{
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return (struct vioapic *)vm->arch_vm.virt_ioapic;
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}
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static void
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vioapic_send_intr(struct vioapic *vioapic, uint32_t pin)
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{
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uint32_t vector, dest, delmode;
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union ioapic_rte rte;
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bool level, phys;
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uint32_t pincount = vioapic_pincount(vioapic->vm);
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if (pin >= pincount) {
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pr_err("vioapic_send_intr: invalid pin number %hhu", pin);
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}
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rte = vioapic->rtbl[pin];
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if ((rte.full & IOAPIC_RTE_INTMASK) == IOAPIC_RTE_INTMSET) {
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: masked", pin);
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return;
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}
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phys = ((rte.full & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
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delmode = (uint32_t)(rte.full & IOAPIC_RTE_DELMOD);
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level = ((rte.full & IOAPIC_RTE_TRGRLVL) != 0UL);
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/* For level trigger irq, avoid send intr if
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* previous one hasn't received EOI
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*/
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if (level) {
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if (vioapic->rtbl[pin].full & IOAPIC_RTE_REM_IRR) {
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return;
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}
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vioapic->rtbl[pin].full |= IOAPIC_RTE_REM_IRR;
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}
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vector = rte.u.lo_32 & IOAPIC_RTE_LOW_INTVEC;
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dest = (uint32_t)(rte.full >> IOAPIC_RTE_DEST_SHIFT);
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vlapic_deliver_intr(vioapic->vm, level, dest, phys,
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delmode, vector, false);
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}
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static void
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vioapic_set_pinstate(struct vioapic *vioapic, uint32_t pin, bool newstate)
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{
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int oldcnt, newcnt;
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bool needintr;
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uint32_t pincount = vioapic_pincount(vioapic->vm);
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if (pin >= pincount) {
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pr_err("vioapic_set_pinstate: invalid pin number %hhu", pin);
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}
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oldcnt = vioapic->acnt[pin];
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if (newstate) {
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vioapic->acnt[pin]++;
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} else {
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vioapic->acnt[pin]--;
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}
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newcnt = vioapic->acnt[pin];
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if (newcnt < 0) {
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pr_err("ioapic pin%hhu: bad acnt %d", pin, newcnt);
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}
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needintr = false;
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if (oldcnt == 0 && newcnt == 1) {
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needintr = true;
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: asserted", pin);
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} else if (oldcnt == 1 && newcnt == 0) {
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: deasserted", pin);
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} else {
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: %s, ignored, acnt %d",
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pin, pinstate_str(newstate), newcnt);
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}
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if (needintr) {
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vioapic_send_intr(vioapic, pin);
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}
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}
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enum irqstate {
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IRQSTATE_ASSERT,
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IRQSTATE_DEASSERT,
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IRQSTATE_PULSE
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};
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static int
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vioapic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate)
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{
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struct vioapic *vioapic;
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uint32_t pin = irq;
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if (pin >= vioapic_pincount(vm)) {
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return -EINVAL;
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}
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vioapic = vm_ioapic(vm);
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VIOAPIC_LOCK(vioapic);
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switch (irqstate) {
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case IRQSTATE_ASSERT:
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vioapic_set_pinstate(vioapic, pin, true);
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break;
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case IRQSTATE_DEASSERT:
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vioapic_set_pinstate(vioapic, pin, false);
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break;
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case IRQSTATE_PULSE:
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vioapic_set_pinstate(vioapic, pin, true);
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vioapic_set_pinstate(vioapic, pin, false);
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break;
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default:
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panic("vioapic_set_irqstate: invalid irqstate %d", irqstate);
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}
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VIOAPIC_UNLOCK(vioapic);
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return 0;
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}
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int
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vioapic_assert_irq(struct vm *vm, uint32_t irq)
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{
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return vioapic_set_irqstate(vm, irq, IRQSTATE_ASSERT);
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}
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int
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vioapic_deassert_irq(struct vm *vm, uint32_t irq)
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{
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return vioapic_set_irqstate(vm, irq, IRQSTATE_DEASSERT);
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}
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int
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vioapic_pulse_irq(struct vm *vm, uint32_t irq)
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{
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return vioapic_set_irqstate(vm, irq, IRQSTATE_PULSE);
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}
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/*
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* Reset the vlapic's trigger-mode register to reflect the ioapic pin
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* configuration.
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*/
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void
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vioapic_update_tmr(struct vcpu *vcpu)
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{
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struct vioapic *vioapic;
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struct acrn_vlapic *vlapic;
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union ioapic_rte rte;
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uint32_t vector, delmode;
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bool level;
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uint32_t pin, pincount;
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vlapic = vcpu->arch_vcpu.vlapic;
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vioapic = vm_ioapic(vcpu->vm);
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VIOAPIC_LOCK(vioapic);
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pincount = vioapic_pincount(vcpu->vm);
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for (pin = 0U; pin < pincount; pin++) {
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rte = vioapic->rtbl[pin];
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level = ((rte.full & IOAPIC_RTE_TRGRLVL) != 0UL);
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/*
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* For a level-triggered 'pin' let the vlapic figure out if
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* an assertion on this 'pin' would result in an interrupt
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* being delivered to it. If yes, then it will modify the
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* TMR bit associated with this vector to level-triggered.
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*/
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delmode = (uint32_t)(rte.full & IOAPIC_RTE_DELMOD);
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vector = rte.u.lo_32 & IOAPIC_RTE_LOW_INTVEC;
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vlapic_set_tmr_one_vec(vlapic, delmode, vector, level);
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}
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vlapic_apicv_batch_set_tmr(vlapic);
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VIOAPIC_UNLOCK(vioapic);
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}
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static uint32_t
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vioapic_indirect_read(struct vioapic *vioapic, uint32_t addr)
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{
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uint32_t regnum;
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uint32_t pin, pincount = vioapic_pincount(vioapic->vm);
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regnum = addr & 0xffU;
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switch (regnum) {
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case IOAPIC_ID:
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return vioapic->id;
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case IOAPIC_VER:
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return (((uint32_t)pincount - 1U) << MAX_RTE_SHIFT) |
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ACRN_IOAPIC_VERSION;
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case IOAPIC_ARB:
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return vioapic->id;
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default:
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/*
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* In this switch statement, regnum shall either be IOAPIC_ID or
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* IOAPIC_VER or IOAPIC_ARB.
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* All the other cases will be handled properly later after this
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* switch statement.
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*/
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break;
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}
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/* redirection table entries */
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if ((regnum >= IOAPIC_REDTBL) &&
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(regnum < (IOAPIC_REDTBL + (pincount * 2U)))) {
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uint32_t addr_offset = regnum - IOAPIC_REDTBL;
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uint32_t rte_offset = addr_offset / 2U;
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pin = rte_offset;
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if ((addr_offset % 2U) != 0U) {
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return vioapic->rtbl[pin].u.hi_32;
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} else {
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return vioapic->rtbl[pin].u.lo_32;
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}
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}
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return 0;
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}
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/* Due to the race between vcpus, ensure to do VIOAPIC_LOCK(vioapic) &
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* VIOAPIC_UNLOCK(vioapic) by caller.
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*/
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static void
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vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
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{
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union ioapic_rte last, new;
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uint64_t changed;
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uint32_t regnum;
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uint32_t pin, pincount = vioapic_pincount(vioapic->vm);
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regnum = addr & 0xffUL;
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switch (regnum) {
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case IOAPIC_ID:
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vioapic->id = data & IOAPIC_ID_MASK;
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break;
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case IOAPIC_VER:
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case IOAPIC_ARB:
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/* readonly */
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break;
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default:
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/*
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* In this switch statement, regnum shall either be IOAPIC_ID or
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* IOAPIC_VER or IOAPIC_ARB.
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* All the other cases will be handled properly later after this
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* switch statement.
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*/
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break;
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}
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/* redirection table entries */
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if ((regnum >= IOAPIC_REDTBL) &&
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(regnum < (IOAPIC_REDTBL + (pincount * 2U)))) {
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uint32_t addr_offset = regnum - IOAPIC_REDTBL;
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uint32_t rte_offset = addr_offset / 2U;
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pin = rte_offset;
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last = vioapic->rtbl[pin];
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new = last;
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if ((addr_offset % 2U) != 0U) {
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new.u.hi_32 = data;
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} else {
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new.u.lo_32 &= RTBL_RO_BITS;
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new.u.lo_32 |= (data & ~RTBL_RO_BITS);
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}
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/* In some special scenarios, the LAPIC somehow hasn't send
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* EOI to IOAPIC which cause the Remote IRR bit can't be clear.
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* To clear it, some OSes will use EOI Register to clear it for
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* 0x20 version IOAPIC, otherwise use switch Trigger Mode to
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* Edge Sensitive to clear it.
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*/
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if ((new.full & IOAPIC_RTE_TRGRLVL) == 0U) {
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new.full &= ~IOAPIC_RTE_REM_IRR;
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}
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changed = last.full ^ new.full;
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/* pin0 from vpic mask/unmask */
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if (pin == 0U && (changed & IOAPIC_RTE_INTMASK) != 0UL) {
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/* mask -> umask */
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if ((last.full & IOAPIC_RTE_INTMASK) != 0UL &&
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((new.full & IOAPIC_RTE_INTMASK) == 0UL)) {
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if ((vioapic->vm->wire_mode ==
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VPIC_WIRE_NULL) ||
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(vioapic->vm->wire_mode ==
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VPIC_WIRE_INTR)) {
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vioapic->vm->wire_mode =
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VPIC_WIRE_IOAPIC;
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dev_dbg(ACRN_DBG_IOAPIC,
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"vpic wire mode -> IOAPIC");
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} else {
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pr_err("WARNING: invalid vpic wire mode change");
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return;
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}
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/* unmask -> mask */
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} else if (((last.full & IOAPIC_RTE_INTMASK) == 0UL) &&
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(new.full & IOAPIC_RTE_INTMASK) != 0UL) {
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if (vioapic->vm->wire_mode ==
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VPIC_WIRE_IOAPIC) {
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vioapic->vm->wire_mode =
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VPIC_WIRE_INTR;
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dev_dbg(ACRN_DBG_IOAPIC,
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"vpic wire mode -> INTR");
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}
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} else {
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/* Can never happen since IOAPIC_RTE_INTMASK
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* is changed. */
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}
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}
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vioapic->rtbl[pin] = new;
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: redir table entry %#lx",
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pin, vioapic->rtbl[pin].full);
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/*
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* If any fields in the redirection table entry (except mask
|
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* or polarity) have changed then rendezvous all the vcpus
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* to update their vlapic trigger-mode registers.
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*/
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if ((changed & NEED_TMR_UPDATE) != 0UL) {
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uint16_t i;
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struct vcpu *vcpu;
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dev_dbg(ACRN_DBG_IOAPIC,
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"ioapic pin%hhu: recalculate vlapic trigger-mode reg",
|
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pin);
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foreach_vcpu(i, vioapic->vm, vcpu) {
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vcpu_make_request(vcpu, ACRN_REQUEST_TMR_UPDATE);
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}
|
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}
|
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|
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/*
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* Generate an interrupt if the following conditions are met:
|
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* - pin is not masked
|
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* - previous interrupt has been EOIed
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* - pin level is asserted
|
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*/
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if ((vioapic->rtbl[pin].full & IOAPIC_RTE_INTMASK) ==
|
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IOAPIC_RTE_INTMCLR &&
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(vioapic->rtbl[pin].full & IOAPIC_RTE_REM_IRR) == 0UL &&
|
||||
(vioapic->acnt[pin] > 0)) {
|
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dev_dbg(ACRN_DBG_IOAPIC,
|
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"ioapic pin%hhu: asserted at rtbl write, acnt %d",
|
||||
pin, vioapic->acnt[pin]);
|
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vioapic_send_intr(vioapic, pin);
|
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}
|
||||
|
||||
/* remap for active: interrupt mask -> unmask
|
||||
* remap for deactive: interrupt mask & vector set to 0
|
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* remap for trigger mode change
|
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* remap for polarity change
|
||||
*/
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if ( (changed & IOAPIC_RTE_INTMASK) != 0UL ||
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(changed & IOAPIC_RTE_TRGRMOD) != 0UL ||
|
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(changed & IOAPIC_RTE_INTPOL ) != 0UL ) {
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||||
|
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/* VM enable intr */
|
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struct ptdev_intx_info intx;
|
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/* NOTE: only support max 256 pin */
|
||||
intx.virt_pin = (uint8_t)pin;
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||||
intx.vpin_src = PTDEV_VPIN_IOAPIC;
|
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ptdev_intx_pin_remap(vioapic->vm, &intx);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
vioapic_mmio_rw(struct vioapic *vioapic, uint64_t gpa,
|
||||
uint32_t *data, bool do_read)
|
||||
{
|
||||
uint32_t offset;
|
||||
|
||||
offset = (uint32_t)(gpa - VIOAPIC_BASE);
|
||||
|
||||
VIOAPIC_LOCK(vioapic);
|
||||
|
||||
/* The IOAPIC specification allows 32-bit wide accesses to the
|
||||
* IOAPIC_REGSEL (offset 0) and IOAPIC_WINDOW (offset 16) registers.
|
||||
*/
|
||||
switch (offset) {
|
||||
case IOAPIC_REGSEL:
|
||||
if (do_read) {
|
||||
*data = vioapic->ioregsel;
|
||||
} else {
|
||||
vioapic->ioregsel = *data & 0xFFU;
|
||||
}
|
||||
break;
|
||||
case IOAPIC_WINDOW:
|
||||
if (do_read) {
|
||||
*data = vioapic_indirect_read(vioapic,
|
||||
vioapic->ioregsel);
|
||||
} else {
|
||||
vioapic_indirect_write(vioapic,
|
||||
vioapic->ioregsel, *data);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (do_read) {
|
||||
*data = 0xFFFFFFFFU;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
VIOAPIC_UNLOCK(vioapic);
|
||||
}
|
||||
|
||||
void
|
||||
vioapic_process_eoi(struct vm *vm, uint32_t vector)
|
||||
{
|
||||
struct vioapic *vioapic;
|
||||
uint32_t pin, pincount = vioapic_pincount(vm);
|
||||
union ioapic_rte rte;
|
||||
|
||||
if (vector < VECTOR_DYNAMIC_START || vector > NR_MAX_VECTOR) {
|
||||
pr_err("vioapic_process_eoi: invalid vector %u", vector);
|
||||
}
|
||||
|
||||
vioapic = vm_ioapic(vm);
|
||||
dev_dbg(ACRN_DBG_IOAPIC, "ioapic processing eoi for vector %u", vector);
|
||||
|
||||
/* notify device to ack if assigned pin */
|
||||
for (pin = 0U; pin < pincount; pin++) {
|
||||
rte = vioapic->rtbl[pin];
|
||||
if (((rte.u.lo_32 & IOAPIC_RTE_LOW_INTVEC) != vector) ||
|
||||
((rte.full & IOAPIC_RTE_REM_IRR) == 0UL)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
ptdev_intx_ack(vm, (uint8_t)pin, PTDEV_VPIN_IOAPIC);
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX keep track of the pins associated with this vector instead
|
||||
* of iterating on every single pin each time.
|
||||
*/
|
||||
VIOAPIC_LOCK(vioapic);
|
||||
for (pin = 0U; pin < pincount; pin++) {
|
||||
rte = vioapic->rtbl[pin];
|
||||
if (((rte.u.lo_32 & IOAPIC_RTE_LOW_INTVEC) != vector) ||
|
||||
((rte.full & IOAPIC_RTE_REM_IRR) == 0UL)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
vioapic->rtbl[pin].full &= (~IOAPIC_RTE_REM_IRR);
|
||||
if (vioapic->acnt[pin] > 0) {
|
||||
dev_dbg(ACRN_DBG_IOAPIC,
|
||||
"ioapic pin%hhu: asserted at eoi, acnt %d",
|
||||
pin, vioapic->acnt[pin]);
|
||||
vioapic_send_intr(vioapic, pin);
|
||||
}
|
||||
}
|
||||
VIOAPIC_UNLOCK(vioapic);
|
||||
}
|
||||
|
||||
void
|
||||
vioapic_reset(struct vioapic *vioapic)
|
||||
{
|
||||
uint32_t pin, pincount;
|
||||
|
||||
/* Initialize all redirection entries to mask all interrupts */
|
||||
pincount = vioapic_pincount(vioapic->vm);
|
||||
for (pin = 0U; pin < pincount; pin++) {
|
||||
vioapic->rtbl[pin].full = MASK_ALL_INTERRUPTS;
|
||||
}
|
||||
vioapic->id = 0U;
|
||||
vioapic->ioregsel = 0U;
|
||||
}
|
||||
|
||||
struct vioapic *
|
||||
vioapic_init(struct vm *vm)
|
||||
{
|
||||
struct vioapic *vioapic;
|
||||
|
||||
vioapic = calloc(1U, sizeof(struct vioapic));
|
||||
ASSERT(vioapic != NULL, "");
|
||||
|
||||
vioapic->vm = vm;
|
||||
spinlock_init(&vioapic->mtx);
|
||||
|
||||
vioapic_reset(vioapic);
|
||||
|
||||
register_mmio_emulation_handler(vm,
|
||||
vioapic_mmio_access_handler,
|
||||
(uint64_t)VIOAPIC_BASE,
|
||||
(uint64_t)VIOAPIC_BASE + VIOAPIC_SIZE,
|
||||
NULL);
|
||||
|
||||
return vioapic;
|
||||
}
|
||||
|
||||
void
|
||||
vioapic_cleanup(struct vioapic *vioapic)
|
||||
{
|
||||
unregister_mmio_emulation_handler(vioapic->vm,
|
||||
(uint64_t)VIOAPIC_BASE,
|
||||
(uint64_t)VIOAPIC_BASE + VIOAPIC_SIZE);
|
||||
free(vioapic);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
vioapic_pincount(struct vm *vm)
|
||||
{
|
||||
if (is_vm0(vm)) {
|
||||
return REDIR_ENTRIES_HW;
|
||||
} else {
|
||||
return VIOAPIC_RTE_NUM;
|
||||
}
|
||||
}
|
||||
|
||||
int vioapic_mmio_access_handler(struct vcpu *vcpu, struct io_request *io_req,
|
||||
__unused void *handler_private_data)
|
||||
{
|
||||
struct vm *vm = vcpu->vm;
|
||||
struct vioapic *vioapic;
|
||||
struct mmio_request *mmio = &io_req->reqs.mmio;
|
||||
uint64_t gpa = mmio->address;
|
||||
int ret = 0;
|
||||
|
||||
vioapic = vm_ioapic(vm);
|
||||
|
||||
/* Note all RW to IOAPIC are 32-Bit in size */
|
||||
if (mmio->size == 4UL) {
|
||||
uint32_t data = (uint32_t)mmio->value;
|
||||
|
||||
if (mmio->direction == REQUEST_READ) {
|
||||
vioapic_mmio_rw(vioapic, gpa, &data, true);
|
||||
mmio->value = (uint64_t)data;
|
||||
|
||||
} else if (mmio->direction == REQUEST_WRITE) {
|
||||
vioapic_mmio_rw(vioapic, gpa, &data, false);
|
||||
|
||||
} else
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
pr_err("All RW to IOAPIC must be 32-bits in size");
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
io_req->processed = REQ_STATE_COMPLETE;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @pre vm->arch_vm.virt_ioapic != NULL
|
||||
* @pre rte != NULL
|
||||
*/
|
||||
void vioapic_get_rte(struct vm *vm, uint32_t pin, union ioapic_rte *rte)
|
||||
{
|
||||
struct vioapic *vioapic;
|
||||
|
||||
vioapic = vm_ioapic(vm);
|
||||
*rte = vioapic->rtbl[pin];
|
||||
}
|
||||
|
||||
#ifdef HV_DEBUG
|
||||
void get_vioapic_info(char *str_arg, int str_max, uint16_t vmid)
|
||||
{
|
||||
char *str = str_arg;
|
||||
int len, size = str_max;
|
||||
union ioapic_rte rte;
|
||||
uint32_t delmode, vector, dest;
|
||||
bool level, phys, remote_irr, mask;
|
||||
struct vm *vm = get_vm_from_vmid(vmid);
|
||||
uint32_t pin, pincount;
|
||||
|
||||
if (vm == NULL) {
|
||||
len = snprintf(str, size,
|
||||
"\r\nvm is not exist for vmid %hu", vmid);
|
||||
size -= len;
|
||||
str += len;
|
||||
goto END;
|
||||
}
|
||||
|
||||
len = snprintf(str, size,
|
||||
"\r\nPIN\tVEC\tDM\tDEST\tTM\tDELM\tIRR\tMASK");
|
||||
size -= len;
|
||||
str += len;
|
||||
|
||||
pincount = vioapic_pincount(vm);
|
||||
rte.full = 0UL;
|
||||
for (pin = 0U; pin < pincount; pin++) {
|
||||
vioapic_get_rte(vm, pin, &rte);
|
||||
mask = ((rte.full & IOAPIC_RTE_INTMASK) == IOAPIC_RTE_INTMSET);
|
||||
remote_irr = ((rte.full & IOAPIC_RTE_REM_IRR) == IOAPIC_RTE_REM_IRR);
|
||||
phys = ((rte.full & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
|
||||
delmode = (uint32_t)(rte.full & IOAPIC_RTE_DELMOD);
|
||||
level = ((rte.full & IOAPIC_RTE_TRGRLVL) != 0UL);
|
||||
vector = rte.u.lo_32 & IOAPIC_RTE_LOW_INTVEC;
|
||||
dest = (uint32_t)(rte.full >> IOAPIC_RTE_DEST_SHIFT);
|
||||
|
||||
len = snprintf(str, size,
|
||||
"\r\n%hhu\t0x%X\t%s\t0x%X\t%s\t%u\t%d\t%d",
|
||||
pin, vector, phys ? "phys" : "logic",
|
||||
dest, level ? "level" : "edge",
|
||||
delmode >> 8U, remote_irr, mask);
|
||||
size -= len;
|
||||
str += len;
|
||||
}
|
||||
END:
|
||||
snprintf(str, size, "\r\n");
|
||||
}
|
||||
#endif /* HV_DEBUG */
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user