diff --git a/hypervisor/arch/x86/guest/virq.c b/hypervisor/arch/x86/guest/virq.c
index 47ec2db93..a408abac9 100644
--- a/hypervisor/arch/x86/guest/virq.c
+++ b/hypervisor/arch/x86/guest/virq.c
@@ -468,25 +468,6 @@ int32_t acrn_handle_pending_request(struct acrn_vcpu *vcpu)
 
 			arch->inject_event_pending = false;
 		} else {
-			/*
-			 * From SDM Vol3 26.3.2.5:
-			 * Once the virtual interrupt is recognized, it will be delivered
-			 * in VMX non-root operation immediately after VM entry(including
-			 * any specified event injection) completes.
-			 *
-			 * So the hardware can handle vmcs event injection and
-			 * evaluation/delivery of apicv virtual interrupts in one time
-			 * vm-entry.
-			 *
-			 * Here to sync the pending interrupts to irr and update rvi if
-			 * needed. And then try to handle vmcs event injection.
-			 */
-			if (is_apicv_advanced_feature_supported() &&
-				bitmap_test_and_clear_lock(ACRN_REQUEST_EVENT, pending_req_bits)) {
-				vlapic = vcpu_vlapic(vcpu);
-				vlapic_apicv_inject_pir(vlapic);
-			}
-
 			/* SDM Vol 3 - table 6-2, inject high priority exception before
 			 * maskable hardware interrupt */
 			if (vcpu_inject_hi_exception(vcpu) == 0) {
@@ -501,6 +482,25 @@ int32_t acrn_handle_pending_request(struct acrn_vcpu *vcpu)
 			}
 		}
 
+		/*
+		 * From SDM Vol3 26.3.2.5:
+		 * Once the virtual interrupt is recognized, it will be delivered
+		 * in VMX non-root operation immediately after VM entry(including
+		 * any specified event injection) completes.
+		 *
+		 * So the hardware can handle vmcs event injection and
+		 * evaluation/delivery of apicv virtual interrupts in one time
+		 * vm-entry.
+		 *
+		 * Here to sync the pending interrupts to irr and update rvi if
+		 * needed. And then try to handle vmcs event injection.
+		 */
+		if (is_apicv_advanced_feature_supported() &&
+			bitmap_test_and_clear_lock(ACRN_REQUEST_EVENT, pending_req_bits)) {
+			vlapic = vcpu_vlapic(vcpu);
+			vlapic_apicv_inject_pir(vlapic);
+		}
+
 		/*
 		 * If "virtual-interrupt delivered" is enabled, CPU will evaluate
 		 * and automatic inject the virtual interrupts in appropriate time.