github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-24 14:33:38 +00:00
Code Issues Projects Releases Wiki Activity

hv: move panic out of hv_main

Browse Source 
We cleanup ASSERT. This serial try to only panic when create
SOS failed.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
This commit is contained in:
Li, Fei1 2018-05-28 10:23:04 +08:00 committed by lijinxia
parent 574bdc3aef
commit fe4484f5a9
2 changed files with 24 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
hypervisor/arch/x86/cpu.c
View File

@ -367,6 +367,7 @@ static void get_cpu_name(void)
void bsp_boot_init(void) void bsp_boot_init(void)
{ {
int ret;
uint64_t start_tsc = rdtsc(); uint64_t start_tsc = rdtsc();
/* Clear BSS */ /* Clear BSS */
@ -541,7 +542,9 @@ void bsp_boot_init(void)
console_setup_timer(); console_setup_timer();
/* Start initializing the VM for this CPU */ /* Start initializing the VM for this CPU */
hv_main(CPU_BOOT_ID); ret = hv_main(CPU_BOOT_ID);
if (ret != 0)
panic("failed to start VM for bsp\n");
/* Control should not come here */ /* Control should not come here */
cpu_dead(CPU_BOOT_ID); cpu_dead(CPU_BOOT_ID);
@ -549,6 +552,7 @@ void bsp_boot_init(void)
void cpu_secondary_init(void) void cpu_secondary_init(void)
{ {
int ret;
/* NOTE: Use of local / stack variables in this function is problematic /* NOTE: Use of local / stack variables in this function is problematic
* since the stack is switched in the middle of the function. For this * since the stack is switched in the middle of the function. For this
* reason, the logical id is only temporarily stored in a static * reason, the logical id is only temporarily stored in a static
@ -605,7 +609,9 @@ void cpu_secondary_init(void)
/* Wait for boot processor to signal all secondary cores to continue */ /* Wait for boot processor to signal all secondary cores to continue */
pcpu_sync_sleep(&pcpu_sync, 0); pcpu_sync_sleep(&pcpu_sync, 0);
hv_main(get_cpu_id()); ret = hv_main(get_cpu_id());
if (ret != 0)
panic("hv_main ret = %d\n", ret);
/* Control will only come here for secondary CPUs not configured for /* Control will only come here for secondary CPUs not configured for
* use or if an error occurs in hv_main * use or if an error occurs in hv_main

22
hypervisor/common/hv_main.c
View File

@ -138,18 +138,28 @@ static bool is_vm0_bsp(int pcpu_id)
int hv_main(int cpu_id) int hv_main(int cpu_id)
{ {
int ret = 0; int ret;
pr_info("%s, Starting common entry point for CPU %d", pr_info("%s, Starting common entry point for CPU %d",
__func__, cpu_id); __func__, cpu_id);
ASSERT(cpu_id < phy_cpu_num, "cpu_id out of range");
ASSERT((uint64_t) cpu_id == get_cpu_id(), if (cpu_id >= phy_cpu_num) {
"cpu_id/tsc_aux mismatch"); pr_err("%s, cpu_id %d out of range %d\n",
__func__, cpu_id, phy_cpu_num);
return -EINVAL;
}
if ((uint32_t) cpu_id != get_cpu_id()) {
pr_err("%s, cpu_id %d mismatch\n", __func__, cpu_id);
return -EINVAL;
}
/* Enable virtualization extensions */ /* Enable virtualization extensions */
ret = exec_vmxon_instr(); ret = exec_vmxon_instr();
ASSERT(ret == 0, "Unable to enable VMX!"); if (ret != 0) {
pr_err("%s, Unable to enable VMX!\n", __func__);
return ret;
}
/* X2APIC mode is disabled by default. */ /* X2APIC mode is disabled by default. */
x2apic_enabled = false; x2apic_enabled = false;
@ -159,7 +169,7 @@ int hv_main(int cpu_id)
default_idle(); default_idle();
return ret; return 0;
} }
int get_vmexit_profile(char *str, int str_max) int get_vmexit_profile(char *str, int str_max)