mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-18 19:57:31 +00:00
hv: vioapic init for SOS VM on platforms with multiple IO-APICs
For SOS VM, when the target platform has multiple IO-APICs, there should be equal number of virtual IO-APICs. This patch adds support for emulating multiple vIOAPICs per VM. Tracked-On: #4151 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Sainath Grandhi
wenlingz
parent
f67ac09141
commit
fe5a108c7b
@ -898,8 +898,13 @@ vlapic_process_eoi(struct acrn_vlapic *vlapic)
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vlapic_update_ppr(vlapic);
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if (bitmap32_test((uint16_t)bitpos, &tmrptr[i].v)) {
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/* hook to vIOAPIC */
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vioapic_process_eoi(vlapic->vm, vector);
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/*
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* Per Intel SDM 10.8.5, Software can inhibit the broadcast of
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* EOI by setting bit 12 of the Spurious Interrupt Vector
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* Register of the LAPIC.
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* TODO: Check if the bit 12 "Suppress EOI Broadcasts" is set.
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*/
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vioapic_broadcast_eoi(vlapic->vm, vector);
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}
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vcpu_make_request(vlapic->vcpu, ACRN_REQUEST_EVENT);
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@ -2513,7 +2518,7 @@ int32_t veoi_vmexit_handler(struct acrn_vcpu *vcpu)
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if (bitmap32_test((uint16_t)(vector & 0x1fU), &tmrptr[idx].v)) {
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/* hook to vIOAPIC */
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vioapic_process_eoi(vlapic->vm, vector);
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vioapic_broadcast_eoi(vlapic->vm, vector);
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}
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TRACE_2L(TRACE_VMEXIT_APICV_VIRT_EOI, vector, 0UL);
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@ -659,7 +659,7 @@ int32_t reset_vm(struct acrn_vm *vm)
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}
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reset_vm_ioreqs(vm);
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vioapic_reset(vm);
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reset_vioapics(vm);
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destroy_secure_world(vm, false);
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vm->sworld_control.flag.active = 0UL;
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vm->state = VM_CREATED;
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@ -73,6 +73,17 @@ uint32_t get_pic_pin_from_ioapic_pin(uint32_t pin_index)
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return pin_id;
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}
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uint8_t get_platform_ioapic_info (struct ioapic_info **plat_ioapic_info)
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{
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*plat_ioapic_info = ioapic_array;
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return ioapic_num;
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}
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uint8_t get_gsi_to_ioapic_index(uint32_t gsi)
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{
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return gsi_table_data[gsi].ioapic_info.index;
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}
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/*
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* @pre gsi < NR_MAX_GSI
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*/
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@ -353,7 +353,7 @@ int32_t hcall_set_irqline(const struct acrn_vm *vm, uint16_t vmid,
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int32_t ret = -1;
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if (!is_poweroff_vm(target_vm) && is_postlaunched_vm(target_vm)) {
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if (ops->gsi < vioapic_pincount(vm)) {
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if (ops->gsi < get_vm_gsicount(vm)) {
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if (ops->gsi < vpic_pincount()) {
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/*
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* IRQ line for 8254 timer is connected to
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@ -905,8 +905,13 @@ int32_t hcall_set_ptdev_intr_info(struct acrn_vm *vm, uint16_t vmid, uint64_t pa
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spinlock_obtain(&vpci->lock);
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vdev = pci_find_vdev(vpci, bdf);
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spinlock_release(&vpci->lock);
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/*
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* TODO: Change the hc_ptdev_irq structure member names
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* virt_pin to virt_gsi
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* phys_pin to phys_gsi
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*/
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if ((vdev != NULL) && (vdev->pdev->bdf.value == irq.phys_bdf)) {
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if ((((!irq.intx.pic_pin) && (irq.intx.virt_pin < vioapic_pincount(target_vm))) ||
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if ((((!irq.intx.pic_pin) && (irq.intx.virt_pin < get_vm_gsicount(target_vm))) ||
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((irq.intx.pic_pin) && (irq.intx.virt_pin < vpic_pincount()))) &&
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is_gsi_valid(irq.intx.phys_pin)) {
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ret = ptirq_add_intx_remapping(target_vm, irq.intx.virt_pin,
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@ -954,8 +959,13 @@ hcall_reset_ptdev_intr_info(struct acrn_vm *vm, uint16_t vmid, uint64_t param)
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spinlock_obtain(&vpci->lock);
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vdev = pci_find_vdev(vpci, bdf);
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spinlock_release(&vpci->lock);
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/*
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* TODO: Change the hc_ptdev_irq structure member names
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* virt_pin to virt_gsi
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* phys_pin to phys_gsi
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*/
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if ((vdev != NULL) && (vdev->pdev->bdf.value == irq.phys_bdf)) {
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if (((!irq.intx.pic_pin) && (irq.intx.virt_pin < vioapic_pincount(target_vm))) ||
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if (((!irq.intx.pic_pin) && (irq.intx.virt_pin < get_vm_gsicount(target_vm))) ||
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((irq.intx.pic_pin) && (irq.intx.virt_pin < vpic_pincount()))) {
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ptirq_remove_intx_remapping(target_vm, irq.intx.virt_pin, irq.intx.pic_pin);
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ret = 0;
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@ -1173,7 +1173,7 @@ static void get_vioapic_info(char *str_arg, size_t str_max, uint16_t vmid)
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uint32_t delmode, vector, dest;
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bool level, phys, remote_irr, mask;
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struct acrn_vm *vm = get_vm_from_vmid(vmid);
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uint32_t gsi, pincount;
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uint32_t gsi, gsi_count;
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if (is_poweroff_vm(vm)) {
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len = snprintf(str, size, "\r\nvm is not exist for vmid %hu", vmid);
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@ -1192,9 +1192,12 @@ static void get_vioapic_info(char *str_arg, size_t str_max, uint16_t vmid)
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size -= len;
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str += len;
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pincount = vioapic_pincount(vm);
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gsi_count = get_vm_gsicount(vm);
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rte.full = 0UL;
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for (gsi = 0U; gsi < pincount; gsi++) {
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for (gsi = 0U; gsi < gsi_count; gsi++) {
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if (is_sos_vm(vm) && (!is_gsi_valid(gsi))) {
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continue;
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}
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vioapic_get_rte(vm, gsi, &rte);
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mask = (rte.bits.intr_mask == IOAPIC_RTE_MASK_SET);
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remote_irr = (rte.bits.remote_irr == IOAPIC_RTE_REM_IRR);
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@ -36,6 +36,7 @@
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#include <ept.h>
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#include <assign.h>
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#include <logmsg.h>
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#include <ioapic.h>
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#define RTBL_RO_BITS ((uint32_t)0x00004000U | (uint32_t)0x00001000U) /*Remote IRR and Delivery Status bits*/
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@ -45,16 +46,16 @@
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#define IOAPIC_ID_MASK 0x0f000000U
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#define MASK_ALL_INTERRUPTS 0x0001000000010000UL
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static inline struct acrn_vioapic *vm_ioapic(const struct acrn_vm *vm)
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static inline struct acrn_vioapics *vm_ioapics(const struct acrn_vm *vm)
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{
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return (struct acrn_vioapic *)&(vm->arch_vm.vioapic);
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return (struct acrn_vioapics *)&(vm->arch_vm.vioapics);
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}
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/**
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* @pre pin < vioapic_pincount(vm)
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* @pre pin < vioapic->nr_pins
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*/
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static void
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vioapic_generate_intr(struct acrn_vioapic *vioapic, uint32_t pin)
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vioapic_generate_intr(struct acrn_single_vioapic *vioapic, uint32_t pin)
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{
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uint32_t vector, dest, delmode;
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union ioapic_rte rte;
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@ -84,10 +85,10 @@ vioapic_generate_intr(struct acrn_vioapic *vioapic, uint32_t pin)
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}
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/**
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* @pre pin < vioapic_pincount(vm)
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* @pre pin < vioapic->nr_pins
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*/
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static void
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vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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vioapic_set_pinstate(struct acrn_single_vioapic *vioapic, uint32_t pin, uint32_t level)
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{
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uint32_t old_lvl;
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union ioapic_rte rte;
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@ -113,6 +114,30 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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}
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}
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static struct acrn_single_vioapic *
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vgsi_to_vioapic_and_vpin(const struct acrn_vm *vm, uint32_t vgsi, uint32_t *vpin)
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{
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struct acrn_single_vioapic *vioapic;
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uint8_t vioapic_index = 0U;
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if (is_sos_vm(vm)) {
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/*
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* Utilize platform ioapic_info for SOS VM
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*/
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vioapic_index = get_gsi_to_ioapic_index(vgsi);
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if (vpin != NULL) {
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*vpin = gsi_to_ioapic_pin(vgsi);
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}
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} else {
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if (vpin != NULL) {
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*vpin = vgsi;
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}
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}
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vioapic = (struct acrn_single_vioapic *)&(vm->arch_vm.vioapics.vioapic_array[vioapic_index]);
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return vioapic;
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}
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/**
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* @brief Set vIOAPIC IRQ line status.
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*
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@ -120,11 +145,11 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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* operation be done with ioapic lock.
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*
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* @param[in] vm Pointer to target VM
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* @param[in] irqline Target IRQ number
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* @param[in] vgsi Target GSI number
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* @param[in] operation Action options: GSI_SET_HIGH/GSI_SET_LOW/
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* GSI_RAISING_PULSE/GSI_FALLING_PULSE
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*
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* @pre irqline < vioapic_pincount(vm)
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* @pre vgsi < get_vm_gsicount(vm)
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* @pre vm != NULL
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* @pre vioapic->ready == true
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* @return None
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@ -132,10 +157,10 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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void
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vioapic_set_irqline_nolock(const struct acrn_vm *vm, uint32_t vgsi, uint32_t operation)
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{
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struct acrn_vioapic *vioapic;
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uint32_t pin = vgsi;
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struct acrn_single_vioapic *vioapic;
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uint32_t pin;
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vioapic = vm_ioapic(vm);
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vioapic = vgsi_to_vioapic_and_vpin(vm, vgsi, &pin);
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switch (operation) {
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case GSI_SET_HIGH:
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@ -164,11 +189,11 @@ vioapic_set_irqline_nolock(const struct acrn_vm *vm, uint32_t vgsi, uint32_t ope
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* @brief Set vIOAPIC IRQ line status.
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*
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* @param[in] vm Pointer to target VM
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* @param[in] irqline Target IRQ number
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* @param[in] vgsi Target GSI number
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* @param[in] operation Action options: GSI_SET_HIGH/GSI_SET_LOW/
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* GSI_RAISING_PULSE/GSI_FALLING_PULSE
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*
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* @pre irqline < vioapic_pincount(vm)
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* @pre vgsi < get_vm_gsicount(vm)
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* @pre vm != NULL
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*
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* @return None
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@ -177,20 +202,21 @@ void
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vioapic_set_irqline_lock(const struct acrn_vm *vm, uint32_t vgsi, uint32_t operation)
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{
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uint64_t rflags;
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uint32_t irqline = vgsi;
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struct acrn_vioapic *vioapic = vm_ioapic(vm);
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struct acrn_single_vioapic *vioapic;
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vioapic = vgsi_to_vioapic_and_vpin(vm, vgsi, NULL);
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if (vioapic->ready) {
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spinlock_irqsave_obtain(&(vioapic->mtx), &rflags);
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vioapic_set_irqline_nolock(vm, irqline, operation);
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vioapic_set_irqline_nolock(vm, vgsi, operation);
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spinlock_irqrestore_release(&(vioapic->mtx), rflags);
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}
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}
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static uint32_t
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vioapic_indirect_read(const struct acrn_vioapic *vioapic, uint32_t addr)
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vioapic_indirect_read(const struct acrn_single_vioapic *vioapic, uint32_t addr)
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{
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uint32_t regnum, ret = 0U;
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uint32_t pin, pincount = vioapic_pincount(vioapic->vm);
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uint32_t pin, pincount = vioapic->nr_pins;
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regnum = addr & 0xffU;
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switch (regnum) {
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@ -229,7 +255,7 @@ vioapic_indirect_read(const struct acrn_vioapic *vioapic, uint32_t addr)
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return ret;
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}
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static inline bool vioapic_need_intr(const struct acrn_vioapic *vioapic, uint16_t pin)
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static inline bool vioapic_need_intr(const struct acrn_single_vioapic *vioapic, uint16_t pin)
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{
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uint32_t lvl;
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union ioapic_rte rte;
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@ -250,11 +276,11 @@ static inline bool vioapic_need_intr(const struct acrn_vioapic *vioapic, uint16_
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* spinlock_irqsave_obtain(&(vioapic->mtx), &rflags) & spinlock_irqrestore_release(&(vioapic->mtx), rflags)
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* by caller.
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*/
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static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr, uint32_t data)
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static void vioapic_indirect_write(struct acrn_single_vioapic *vioapic, uint32_t addr, uint32_t data)
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{
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union ioapic_rte last, new, changed;
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uint32_t regnum;
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uint32_t pin, pincount = vioapic_pincount(vioapic->vm);
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uint32_t pin, pincount = vioapic->nr_pins;
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regnum = addr & 0xffUL;
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switch (regnum) {
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@ -332,7 +358,8 @@ static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
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if ((new.bits.intr_mask == IOAPIC_RTE_MASK_CLR) || (last.bits.intr_mask == IOAPIC_RTE_MASK_CLR)) {
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/* VM enable intr */
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/* NOTE: only support max 256 pin */
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(void)ptirq_intx_pin_remap(vioapic->vm, pin, INTX_CTLR_IOAPIC);
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(void)ptirq_intx_pin_remap(vioapic->vm, vioapic->gsi_base + pin, INTX_CTLR_IOAPIC);
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}
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/*
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@ -352,7 +379,7 @@ static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
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}
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static void
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vioapic_mmio_rw(struct acrn_vioapic *vioapic, uint64_t gpa,
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vioapic_mmio_rw(struct acrn_single_vioapic *vioapic, uint64_t gpa,
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uint32_t *data, bool do_read)
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{
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uint32_t offset;
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@ -396,11 +423,10 @@ vioapic_mmio_rw(struct acrn_vioapic *vioapic, uint64_t gpa,
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* @pre vm != NULL
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* @pre vioapic->ready == true
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*/
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void
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vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
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static void
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vioapic_process_eoi(struct acrn_single_vioapic *vioapic, uint32_t vector)
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{
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struct acrn_vioapic *vioapic;
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uint32_t pin, pincount = vioapic_pincount(vm);
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uint32_t pin, pincount = vioapic->nr_pins;
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union ioapic_rte rte;
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uint64_t rflags;
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@ -408,7 +434,6 @@ vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
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pr_err("vioapic_process_eoi: invalid vector %u", vector);
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}
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vioapic = vm_ioapic(vm);
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dev_dbg(DBG_LEVEL_VIOAPIC, "ioapic processing eoi for vector %u", vector);
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/* notify device to ack if assigned pin */
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@ -419,7 +444,7 @@ vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
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continue;
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}
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ptirq_intx_ack(vm, pin, INTX_CTLR_IOAPIC);
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ptirq_intx_ack(vioapic->vm, vioapic->gsi_base + pin, INTX_CTLR_IOAPIC);
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}
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/*
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@ -444,14 +469,28 @@ vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
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spinlock_irqrestore_release(&(vioapic->mtx), rflags);
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}
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void
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vioapic_reset(struct acrn_vm *vm)
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void vioapic_broadcast_eoi(const struct acrn_vm *vm, uint32_t vector)
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{
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struct acrn_single_vioapic *vioapic;
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uint8_t vioapic_index;
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/*
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* For platforms with multiple IO-APICs, EOI message from LAPIC is
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* broadcast to all IO-APICs. Emulating the same behavior here.
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*/
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for (vioapic_index = 0U; vioapic_index < vm->arch_vm.vioapics.ioapic_num; vioapic_index++) {
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vioapic = &(vm_ioapics(vm)->vioapic_array[vioapic_index]);
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vioapic_process_eoi(vioapic, vector);
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}
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}
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static void reset_one_vioapic(struct acrn_single_vioapic *vioapic)
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{
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uint32_t pin, pincount;
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struct acrn_vioapic *vioapic = vm_ioapic(vm);
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|
||||
/* Initialize all redirection entries to mask all interrupts */
|
||||
pincount = vioapic_pincount(vm);
|
||||
pincount = vioapic->nr_pins;
|
||||
for (pin = 0U; pin < pincount; pin++) {
|
||||
vioapic->rtbl[pin].full = MASK_ALL_INTERRUPTS;
|
||||
}
|
||||
@ -459,35 +498,80 @@ vioapic_reset(struct acrn_vm *vm)
|
||||
vioapic->ioregsel = 0U;
|
||||
}
|
||||
|
||||
void reset_vioapics(const struct acrn_vm *vm)
|
||||
{
|
||||
struct acrn_vioapics *vioapics = vm_ioapics(vm);
|
||||
uint8_t vioapic_index;
|
||||
|
||||
for (vioapic_index = 0U; vioapic_index < vioapics->ioapic_num; vioapic_index++) {
|
||||
reset_one_vioapic(&vioapics->vioapic_array[vioapic_index]);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
vioapic_init(struct acrn_vm *vm)
|
||||
{
|
||||
vm->arch_vm.vioapic.vm = vm;
|
||||
spinlock_init(&(vm->arch_vm.vioapic.mtx));
|
||||
struct ioapic_info *platform_ioapic_info;
|
||||
uint8_t platform_ioapic_num;
|
||||
uint8_t vioapic_index;
|
||||
struct acrn_single_vioapic *vioapic;
|
||||
|
||||
vm->arch_vm.vioapic.base_addr = VIOAPIC_BASE;
|
||||
if (is_sos_vm(vm)) {
|
||||
vm->arch_vm.vioapic.nr_pins = REDIR_ENTRIES_HW;
|
||||
platform_ioapic_num = get_platform_ioapic_info(&platform_ioapic_info);
|
||||
vm->arch_vm.vioapics.ioapic_num = platform_ioapic_num;
|
||||
for (vioapic_index = 0U; vioapic_index < platform_ioapic_num; vioapic_index++) {
|
||||
vioapic = &vm->arch_vm.vioapics.vioapic_array[vioapic_index];
|
||||
spinlock_init(&(vioapic->mtx));
|
||||
vioapic->nr_pins = platform_ioapic_info[vioapic_index].nr_pins;
|
||||
vioapic->base_addr = platform_ioapic_info[vioapic_index].addr;
|
||||
vioapic->gsi_base = platform_ioapic_info[vioapic_index].gsi_base;
|
||||
|
||||
vioapic->vm = vm;
|
||||
reset_one_vioapic(vioapic);
|
||||
|
||||
register_mmio_emulation_handler(vm,
|
||||
vioapic_mmio_access_handler,
|
||||
(uint64_t)vioapic->base_addr,
|
||||
(uint64_t)vioapic->base_addr + VIOAPIC_SIZE,
|
||||
(void *)vioapic, false);
|
||||
ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
|
||||
(uint64_t)vioapic->base_addr, VIOAPIC_SIZE);
|
||||
vioapic->ready = true;
|
||||
}
|
||||
/*
|
||||
* Maximum number of GSI is computed as GSI base of the IOAPIC i.e. enumerated last in ACPI MADT
|
||||
* plus the number of interrupt pins of that IOAPIC.
|
||||
*/
|
||||
vm->arch_vm.vioapics.nr_gsi = platform_ioapic_info[platform_ioapic_num - 1U].gsi_base +
|
||||
platform_ioapic_info[platform_ioapic_num - 1U].nr_pins;
|
||||
} else {
|
||||
vm->arch_vm.vioapic.nr_pins = VIOAPIC_RTE_NUM;
|
||||
vm->arch_vm.vioapics.ioapic_num = 1U;
|
||||
vioapic = &vm->arch_vm.vioapics.vioapic_array[0U];
|
||||
spinlock_init(&(vioapic->mtx));
|
||||
vioapic->nr_pins = VIOAPIC_RTE_NUM;
|
||||
vioapic->base_addr = VIOAPIC_BASE;
|
||||
vioapic->gsi_base = 0U;
|
||||
vioapic->vm = vm;
|
||||
reset_one_vioapic(&vm->arch_vm.vioapics.vioapic_array[0U]);
|
||||
|
||||
|
||||
register_mmio_emulation_handler(vm,
|
||||
vioapic_mmio_access_handler,
|
||||
(uint64_t)vioapic->base_addr,
|
||||
(uint64_t)vioapic->base_addr + VIOAPIC_SIZE,
|
||||
(void *)vioapic, false);
|
||||
ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
|
||||
(uint64_t)vioapic->base_addr, VIOAPIC_SIZE);
|
||||
vioapic->ready = true;
|
||||
|
||||
vm->arch_vm.vioapics.nr_gsi = VIOAPIC_RTE_NUM;
|
||||
}
|
||||
|
||||
vioapic_reset(vm);
|
||||
|
||||
register_mmio_emulation_handler(vm,
|
||||
vioapic_mmio_access_handler,
|
||||
(uint64_t)vm->arch_vm.vioapic.base_addr,
|
||||
(uint64_t)vm->arch_vm.vioapic.base_addr + VIOAPIC_SIZE,
|
||||
(void *)&vm->arch_vm.vioapic, false);
|
||||
ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
|
||||
(uint64_t)vm->arch_vm.vioapic.base_addr, VIOAPIC_SIZE);
|
||||
vm->arch_vm.vioapic.ready = true;
|
||||
}
|
||||
|
||||
uint32_t
|
||||
vioapic_pincount(const struct acrn_vm *vm)
|
||||
get_vm_gsicount(const struct acrn_vm *vm)
|
||||
{
|
||||
return vm->arch_vm.vioapic.nr_pins;
|
||||
return vm->arch_vm.vioapics.nr_gsi;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -496,7 +580,7 @@ vioapic_pincount(const struct acrn_vm *vm)
|
||||
*/
|
||||
int32_t vioapic_mmio_access_handler(struct io_request *io_req, void *handler_private_data)
|
||||
{
|
||||
struct acrn_vioapic *vioapic = (struct acrn_vioapic *)handler_private_data;
|
||||
struct acrn_single_vioapic *vioapic = (struct acrn_single_vioapic *)handler_private_data;
|
||||
struct mmio_request *mmio = &io_req->reqs.mmio;
|
||||
uint64_t gpa = mmio->address;
|
||||
int32_t ret = 0;
|
||||
@ -522,14 +606,15 @@ int32_t vioapic_mmio_access_handler(struct io_request *io_req, void *handler_pri
|
||||
}
|
||||
|
||||
/**
|
||||
* @pre vm->arch_vm.vioapic != NULL
|
||||
* @pre vm->arch_vm.vioapics != NULL
|
||||
* @pre vgsi < get_vm_gsicount(vm)
|
||||
* @pre rte != NULL
|
||||
*/
|
||||
void vioapic_get_rte(const struct acrn_vm *vm, uint32_t vgsi, union ioapic_rte *rte)
|
||||
{
|
||||
struct acrn_vioapic *vioapic;
|
||||
uint32_t pin = vgsi;
|
||||
struct acrn_single_vioapic *vioapic;
|
||||
uint32_t pin;
|
||||
vioapic = vgsi_to_vioapic_and_vpin(vm, vgsi, &pin);
|
||||
|
||||
vioapic = vm_ioapic(vm);
|
||||
*rte = vioapic->rtbl[pin];
|
||||
}
|
||||
|
||||
@ -107,7 +107,7 @@ struct vm_arch {
|
||||
void *sworld_eptp;
|
||||
struct memory_ops ept_mem_ops;
|
||||
|
||||
struct acrn_vioapic vioapic; /* Virtual IOAPIC base address */
|
||||
struct acrn_vioapics vioapics; /* Virtual IOAPIC/s */
|
||||
struct acrn_vpic vpic; /* Virtual PIC */
|
||||
#ifdef CONFIG_HYPERV_ENABLED
|
||||
struct acrn_hyperv hyperv;
|
||||
|
||||
@ -26,6 +26,8 @@ uint32_t gsi_to_ioapic_pin(uint32_t gsi);
|
||||
int32_t init_ioapic_id_info(void);
|
||||
uint8_t ioapic_irq_to_ioapic_id(uint32_t irq);
|
||||
|
||||
uint8_t get_platform_ioapic_info (struct ioapic_info **plat_ioapic_info);
|
||||
|
||||
/**
|
||||
* @defgroup ioapic_ext_apis IOAPIC External Interfaces
|
||||
*
|
||||
@ -108,6 +110,7 @@ struct gsi_table {
|
||||
|
||||
void *gsi_to_ioapic_base(uint32_t gsi);
|
||||
uint32_t get_max_nr_gsi(void);
|
||||
uint8_t get_gsi_to_ioapic_index(uint32_t gsi);
|
||||
uint32_t get_pic_pin_from_ioapic_pin(uint32_t pin_index);
|
||||
bool is_gsi_valid(uint32_t gsi);
|
||||
#endif /* IOAPIC_H */
|
||||
|
||||
@ -48,11 +48,16 @@
|
||||
|
||||
#define IOAPIC_RTE_LOW_INTVEC ((uint32_t)IOAPIC_RTE_INTVEC)
|
||||
|
||||
struct acrn_vioapic {
|
||||
struct acrn_vm *vm;
|
||||
/*
|
||||
* id field is used to emulate the IOAPIC_ID register of vIOAPIC
|
||||
*/
|
||||
|
||||
struct acrn_single_vioapic {
|
||||
spinlock_t mtx;
|
||||
struct acrn_vm *vm;
|
||||
uint32_t base_addr;
|
||||
uint32_t nr_pins;
|
||||
uint32_t gsi_base;
|
||||
uint32_t id;
|
||||
bool ready;
|
||||
uint32_t ioregsel;
|
||||
@ -61,8 +66,19 @@ struct acrn_vioapic {
|
||||
uint64_t pin_state[STATE_BITMAP_SIZE];
|
||||
};
|
||||
|
||||
void vioapic_init(struct acrn_vm *vm);
|
||||
void vioapic_reset(struct acrn_vm *vm);
|
||||
/*
|
||||
* ioapic_num represents the number of IO-APICs emulated for the VM.
|
||||
* nr_gsi represents the maximum number of GSI emulated for the VM.
|
||||
*/
|
||||
struct acrn_vioapics {
|
||||
uint8_t ioapic_num;
|
||||
uint32_t nr_gsi;
|
||||
struct acrn_single_vioapic vioapic_array[CONFIG_MAX_IOAPIC_NUM];
|
||||
};
|
||||
|
||||
void dump_vioapic(struct acrn_vm *vm);
|
||||
void vioapic_init(struct acrn_vm *vm);
|
||||
void reset_vioapics(const struct acrn_vm *vm);
|
||||
|
||||
|
||||
/**
|
||||
@ -102,8 +118,8 @@ void vioapic_set_irqline_lock(const struct acrn_vm *vm, uint32_t vgsi, uint32_t
|
||||
*/
|
||||
void vioapic_set_irqline_nolock(const struct acrn_vm *vm, uint32_t vgsi, uint32_t operation);
|
||||
|
||||
uint32_t vioapic_pincount(const struct acrn_vm *vm);
|
||||
void vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector);
|
||||
uint32_t get_vm_gsicount(const struct acrn_vm *vm);
|
||||
void vioapic_broadcast_eoi(const struct acrn_vm *vm, uint32_t vector);
|
||||
void vioapic_get_rte(const struct acrn_vm *vm, uint32_t vgsi, union ioapic_rte *rte);
|
||||
int32_t vioapic_mmio_access_handler(struct io_request *io_req, void *handler_private_data);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user