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Refine the BSP/AP boot flowchart to match BIOS boot flow

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This is only for the debug purpose. It is still unclear whether it can work on
ICL.

WhiskyLake BIOS will start APs and then each AP will call mwait to wait for BSP to
write monitor memory location to wake them up. Currently the hypervisor
will send SIPI to each AP and re-initialize them after the hypervisor
boots up. So APs can't respond to the wakeup requests from BSP anymore.

Fix: the hypervisor should send SIPI to the APs only after BIOS wakes up the AP.

Signed-off-by: Jack Ren <jack.ren@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
This commit is contained in:
Jack Ren 2019-05-15 13:55:15 +08:00 committed by Zhao Yakui
parent 7e34be2d09
commit ff9d667b49
2 changed files with 20 additions and 1 deletions
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11
hypervisor/arch/x86/cpu.c
View File

@ -232,11 +232,12 @@ void init_pcpu_post(uint16_t pcpu_id)
ptdev_init();
/* Start all secondary cores */
#if 0
startup_paddr = prepare_trampoline();
if (!start_pcpus(AP_MASK)) {
panic("Failed to start all secondary cores!");
}
#endif
ASSERT(get_pcpu_id() == BOOT_CPU_ID, "");
} else {
pr_dbg("Core %hu is up", pcpu_id);
@ -313,6 +314,14 @@ bool start_pcpus(uint64_t mask)
uint16_t pcpu_id = get_pcpu_id();
uint64_t expected_start_mask = mask;
if ((pcpu_active_bitmap & mask) == mask)
return 1;
#if 1
if (startup_paddr == 0)
startup_paddr = prepare_trampoline();
#endif
/* secondary cpu start up will wait for pcpu_sync -> 0UL */
atomic_store64(&pcpu_sync, 1UL);

10
hypervisor/arch/x86/guest/vlapic.c
View File

@ -1201,6 +1201,7 @@ vlapic_process_init_sipi(struct acrn_vcpu* target_vcpu, uint32_t mode,
target_vcpu->arch.nr_sipi = 1U;
}
} else if (mode == APIC_DELMODE_STARTUP) {
/* Ignore SIPIs in any state other than wait-for-SIPI */
if ((target_vcpu->state == VCPU_INIT) &&
(target_vcpu->arch.nr_sipi != 0U)) {
@ -1259,6 +1260,11 @@ static void vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
} else if (((shorthand == APIC_DEST_SELF) || (shorthand == APIC_DEST_ALLISELF))
&& ((mode == APIC_DELMODE_NMI) || (mode == APIC_DELMODE_INIT)
|| (mode == APIC_DELMODE_STARTUP))) {
#if 1
/* Start all secondary cores */
start_pcpus(AP_MASK);
#endif
dev_dbg(ACRN_DBG_LAPIC, "Invalid ICR value");
} else {
@ -1268,6 +1274,10 @@ static void vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
switch (shorthand) {
case APIC_DEST_DESTFLD:
#if 1
/* Start all secondary cores */
start_pcpus(AP_MASK);
#endif
vlapic_calc_dest(vlapic->vm, &dmask, is_broadcast, dest, phys, false);
break;
case APIC_DEST_SELF: