1.Refine cpu affinity in hybrid rt xmls for whl-ipc-i5/7
2.Refine guest flag for hybrid rt xmls for whl-ipc-i5/7
Tracked-On: #5081
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
There is some macro defined in misc_cfg.h while CAT/MBA enabled.
include the missing header to solve build issue.
Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Now the hypervisor configuration source code layout is changed, so acrn-config
need to change accordingly to make sure XML based configuration build success;
Tracked-On: #5077
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The make command is same as old configs layout:
under acrn-hypervisor folder:
make hypervisor BOARD=xxx SCENARIO=xxx [TARGET_DIR]=xxx [RELEASE=x]
under hypervisor folder:
make BOARD=xxx SCENARIO=xxx [TARGET_DIR]=xxx [RELEASE=x]
if BOARD/SCENARIO parameter is not specified, the default will be:
BOARD=nuc7i7dnb SCENARIO=industry
Tracked-On: #5077
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
1.Add UUID for Pre-launched RT VM.
2.Add hybrid_rt.xml for whl-ipc-i7/i5 and also add template Pre-Launched
RT sample xml.
3.Refine sanity check for load_kern_addr/entry.
Tracked-On: #5081
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Config tool should keep aligning with Kconfig default value for
MAX_MSIX_TABLE_NUM.
Note: Remain the same configuration for the board which does not have
PCIe slot or NVME slot.
Tracked-On: #4994
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
1.add max MSI-X table number in board xmls.
2.leave MAX_MSIX_TABLE_NUM item to blank.
Tracked-On: #4994
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Detect and get MSI-X table number in board xmls.
Parse and generate the number for board config while 'MAX_MSIX_TABLE_NUM'
item is blank.
Tracked-On: #4994
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
MBA_DELAY/CLOS_MASK show be exposed only if "MBA"/"L2" or "L3" existed
in rdt resource supoorted in board xml;
The default value of MBA_DELAY is 0;
The numbers of MAB_DELAY/CLOS_MASK entries is determined by:
If CDP is not enabled, the number of entries for CLOS_MASK and MBA_DELAY
is the min of CLOS_MAX of all RDT resources;
If CDP is enabled, divide the CLOS_MAX values for L3 and L2 resources
by 2 and then find the min of all RDT resources to get common_clos_max,
the number of entries for CLOS_MASK is common_clos_max*2,
the number of entries for MBA_DELAY is comm_clos_max.
Tracked-On: #4943
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
The pci.ids database should be already prepared while tools of 'lspci'
were correctly installed and this check for pci.ids should be removed.
Tracked-On: #4989
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
For the base of vuart 1 is not an invalid com base, the tools will check
the target vuart id and it's VM id if matches the other VM's. If they do
not match the error message will report to re-configuration.
Tracked-On: #4991
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch adds support to configure MBA delay values from
scenario xml files just as it is done for CAT mask. This will
improve user experience when configuring RDT resource mask
values.
Tracked-On: #4943
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
There are three TSN devices on EHL CRB, and each of them need 32
vectors.
In order to support TSN devices, increase msix table size and irte
size.
Tracked-On: #4831
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
1.Refinement GVT args for SOS kernel cmdline in scenario config xmls.
2.Refinement GVT args for launch UOS script in launch config xmls.
Tracked-On: #4869
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.Update efi bootloader image file path for Yocto rootfs.
2.Remove empty check for UEFI OS loader name.
Tracked-On: #4868
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Currently, MMIO PCI BDF of ttyS was indexed by IRQ, but it may found
the wrong BDF when the IRQ was shared and it is not expected. So, the
patch uses the MMIO base to query /proc/iomem to find BDF, the waring
will get if BDF is not present in iomem.
Tracked-On: #4862
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
RDT config item is located in the 5rd layer of scenario config;
the number of CLOS_MASK config is dynamically obtained by the rdt
resource clos max in the board config;
the vcpu_clos config is dynamically added or removed when the
pcpu_id config is added or removed;
the drop-down list of vcpu_clos config is reduced by half when
CDP_ENABLED=y.
Tracked-On: #4860
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
1.Add parser and sanity check for RDT_ENABLED/CDP_ENABLED/CLOS_MASK.
2.Skip to generate RDT inforamtion when HW not support RDT or usr
select 'n' to disable RDT feature.
3.Add contiguous bit 1 check for CLOS_MASK.
Tracked-On: #4860
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.Add RDT feature in scenario xmls, add set RDT_ENABLED=y, CDP_ENABLED=n
by default for industry scenario if HW support RDT.
2.Add CLOS_MASK in xmls to configurable and set them to '0xff' by
default if HW support RDT.
3.Remove configurable="0" of clos for PRE launched VM and POST VM, currently,
remain configurable="0" for SOS VM.
4.Add vcpu_clos to match the pcpu_id number, and set vcpu_clos to 0.
Tracked-On: #4860
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch adds xml file, both board as well scenario files
that are need to run ACRN on top of QEMU as a nested hypervisor.
Currently support is only for SDC scenario.
Tracked-On: #3198
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch sets defaults similar to generic platform configuration
when leaf features like PM_INFO, S3_INFO, S5_INFO, DRHD_INFO, CPU_BRAND,
CX_INFO, PX_INFO, MMCFG_BASE_INFO are not generated via either target
offline tool or user supplies empty field in case of emulation.
Tracked-On: #3198
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Remove pre-launched VM console setting in scenario xml and leave it
configured in bootargs directly.
Tracked-On: #4808
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The bootarg of rootfs for pre-launched VM is for Linux only and it
should not limited to physical block device which is selectable from
native rootfs list, it might be a USB or RAM device that "X" is variable
in root=/dev/sdX or /dev/ramX. So remove the rootfs setting in XML and
leave it configured in kernel bootargs directly.
Given the SOS must be Linux and its rootfs must be a physical block
device, rootfs item tag is still reserved in xml for SOS VM section.
Tracked-On: #4808
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
remove configurable="0" for hybrid scenario pci_devs of Pre Launched VM.
Tracked-On: #4808
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
With current acrn-config code, there would be no pci_dev.c generated
if no PCI devices were selected. This would cause a bug for logical_partition
scenario because of an old pci_dev.c is already in the folder and involved
for compiling. The configure tool should override the pci_dev.c, in this case,
to avoid building error.
Tracked-On: #4813
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
As VUART is not supported PCI VUART, use native PCI ttySn's IRQ for
VUART1 would cause communication failed, allocate a free IRQ for it.
Tracked-On: #4798
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Use post_vm_id$(relative id) to identify each post-launched VM to
make sure simultaneous launching successfully.
Tracked-On: #4797
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
