This patch integrates RISC-V with the common IRQ framework:
- Register software and timer interrupt handlers via request_irq().
- Refine dispatch_interrupt() to handle interrupts via do_irq().
Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
There are two reasons to use inline functions and numbered-CSR
instead of simply string concat.
1, With old style, CSR names have to be written in lower cases
and cannot prefix anything. This sometimes causes confusion with
variables. For example, csr_write(sstatus, sstatus). Changing to
inline function with MACROs can reduce confusion:
csr_write(CSR_SSTATUS, sstatus)
2, Using number macros allows us to manage CSRs in a more organized
way. We can now put CSR names in variables or arrays and access them
using variables instead of just string names.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This patch implements risc-v specific timer codes. Basically,
risc-v adapts to acrn timer framework with some specific
behaviors. So far, it enables sstc support in h-mode.
Tracked-On: #8792
Signed-off-by: Haicheng Li <haicheng.li@outlook.com>
Co-developed-by: Yong Li <yong.li@intel.com>
Signed-off-by: Yong Li <yong.li@intel.com>
Co-developed-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
