Commit Graph

15 Commits

Author SHA1 Message Date
Haoyu Tang
730f11e4c9 hv: riscv initialize VM time offset and vcpu timer
Initialize the VM's time_delta to provide a consistent time offset for
guests, and properly initialize vcpu timer-related CSRs (htimedelta and
vstimecmp) to enable guest timer virtualization.

Changes:
- Add time_delta field to vm_arch structure to track VM time offset
- Initialize time_delta to -cpu_ticks() at VM creation, making
  guest time start from 0
- Save/restore htimedelta CSR in vcpu load/unload paths
- Initialize vcpu's htimedelta from VM's time_delta
- Reset vstimecmp to invalid value (0xffffffffffffffff) on vcpu reset
- Add SSTC (Sstc extension) capability check

Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-12-26 07:57:51 +08:00
Haoyu Tang
d6b6dc3bc0 hv: riscv improve vSBI base extension implementation
Replace SBI passthrough with proper virtualization of base extension
queries. For the Service VM, forward actual machine vendor/arch/impl
IDs from the underlying SBI. For guest VMs, provide dummy ACRN-specific
IDs to maintain isolation.

Changes:
- Return vSBI spec version 2.0 for GET_SPEC_VERSION
- Return ACRN implementation ID (55) and version for GET_IMP_ID/GET_IMP_VERSION
- Forward real mvendorid/marchid/mimpid to Service VM
- Provide dummy vendor/arch/impl IDs (0/0/0) to guest VMs
- Store machine IDs in vm_arch structure during VM initialization
- Remove unnecessary SBI passthrough for base extension queries

This provides better isolation and control over the virtual SBI
interface exposed to guests.

Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-12-26 07:57:51 +08:00
Jian Jun Chen
75a932eeab hv: riscv: add virtual interrupt injection support
Add virtual interrupt injection infrastructure for RISC-V hypervisor.
Implement vcpu_set_intr() and vcpu_clear_intr() to manage virtual
interrupt pending state by updating irqs_pending bitmap.
Add vcpu_inject_pending_intr() to inject pending interrupts into
VS-mode by updating HVIP CSR with atomic operations.

Tracked-On: #8844
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-11-25 15:46:29 +08:00
Jian Jun Chen
b3fa6bbced hv: riscv: implement virtual exception handling
Add virtual exception handling infrastructure for RISC-V hypervisor
and enables proper virtualization of RISC-V exceptions by allowing
the hypervisor to inject exceptions into guest VS-mode.
- Implement vcpu_set_trap() to inject traps to VS-mode
- Implement vcpu_queue_exception() to queue exceptions for vCPU injection
- Process pending exception requests in riscv_process_vcpu_requests()

v1->v2:
change vcpu_redirect_trap -> vcpu_set_trap

Tracked-On: #8844
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-11-25 15:46:29 +08:00
Yifan Liu
7388ad45b3 hv: riscv: Add ACRN specific SBI extension skeleton
This is used to implement hypercall in the future.

Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-11-14 10:44:41 +08:00
Yifan Liu
471fb85ba9 hv: riscv: Add dummy vsbi base implementation
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-11-14 10:44:41 +08:00
Haicheng Li
35f9680d30 hv: riscv: Add initial vsbi framework
Adds initial vsbi framework.

Tracked-On: #8841
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-11-14 10:44:41 +08:00
Yifan Liu
8c2e8a6b5d hv: riscv: Add initial vcpu and vcpu exit implementation
Unlike x86 which explicitly distinguishes guest traps and host traps (VM
exits vs. IDT trap gates), risc-v unifies them to a single trap gate
with bits in multiple CSRs representing the privilege mode before the
trap. This commit follows this design.

Due to this change the arch_vcpu_thread in risc-v was basically
abandoned, and used only as a first-time entry point to guest, with the
rest of the original x86 arch_vcpu_thread being re-implemented following
above single-entry design.

Save/restore routine is also being re-implemented to account for
both hs-mode traps and v-mode traps. sscratch is used to mark the place
where the context is being saved to/restored from. When sscratch is
zero at the time of the trap, the context is saved into host stack.
When sscratch is non-zero, the context is saved to vcpu->arch.regs
(similar for restore).

Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-11-14 10:44:41 +08:00
Yifan Liu
0e333ca422 hv: riscv: Add skeleton vcpu and vm to enable RISC-V build
This commit also removes dummy files added in early development stage.

Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-10-30 13:30:32 +08:00
Yifan Liu
43a09e86a7 hv: host_pm: Move two common APIs to common scope
Move shutdown_system to common (and rename to shutdown_host)
Move reset_host to common

Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-10-30 13:30:32 +08:00
Yifan Liu
127c2074a0 hv: vm: Move some common helpers to common scope
No logic change. Only movement.

Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-10-30 13:30:32 +08:00
Yifan Liu
688741074f hv: vm: Move vm common parts under common/vm.h (data structure)
This commit moves struct acrn_vm under common header vm.h, and move some
x86-specific members of struct acrn_vm into arch_vm. This commit focuses
on struct cleanup only. API cleanup will be in future patch series.

The affected members are:
e820_entry_num
e820_entries
wire_mode
wbinvd_lock
vlapic_mode_lock
vcpuid_entry_nr
vcpuid_level
vcpuid_xlevel
vcpuid_entries
reset_control
pm
sworld_control
sworld_snapshot
intr_inject_delay_delta

Moved to common vm.h:
ept_lock -> rename to stg2pt_lock
ept_pgtable -> rename to stg2_pgtable
nworld_eptp -> rename to root_stg2ptp
emul_mmio_lock
nr_emul_mmio_regions
emul_mmio
emul_pio

To avoid circular dependency, some in-header helpers are also moved into
common vm.h.

Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-10-30 13:30:32 +08:00
Fei Li
f687574a58 vuart: add dummy vuart for risc-v
vUART will not enable before VM could be created.

Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-10-14 14:45:12 +08:00
Xue Bosheng
6de0e4b681 hv: add dummy function for riscv support
add dummy function "need_offline", "need_shutdown_vm", "shutdown_vm_from_idle"
to support riscv.

Tracked-On: #8812
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-09-30 12:31:07 +08:00
hangliu1
286c383b53 hv: multiarch: riscv: add dummy header for riscv
add dummy headrer file for early compile, should be replaced totally later.

Tracked-On: #8801
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-09-19 15:04:55 +08:00