Yifan Liu
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0e333ca422
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hv: riscv: Add skeleton vcpu and vm to enable RISC-V build
This commit also removes dummy files added in early development stage.
Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
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2025-10-30 13:30:32 +08:00 |
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