Unlike x86 which explicitly distinguishes guest traps and host traps (VM
exits vs. IDT trap gates), risc-v unifies them to a single trap gate
with bits in multiple CSRs representing the privilege mode before the
trap. This commit follows this design.
Due to this change the arch_vcpu_thread in risc-v was basically
abandoned, and used only as a first-time entry point to guest, with the
rest of the original x86 arch_vcpu_thread being re-implemented following
above single-entry design.
Save/restore routine is also being re-implemented to account for
both hs-mode traps and v-mode traps. sscratch is used to mark the place
where the context is being saved to/restored from. When sscratch is
zero at the time of the trap, the context is saved into host stack.
When sscratch is non-zero, the context is saved to vcpu->arch.regs
(similar for restore).
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This patch integrates RISC-V with the common IRQ framework:
- Register software and timer interrupt handlers via request_irq().
- Refine dispatch_interrupt() to handle interrupts via do_irq().
Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This patch implements interrupt initialization and the basic
exception/interrupt handling flow on RISC-V.
init_interrupt() needs to be invoked during CPU initialization to
set up the trap vector and enable the interrupt.
RISC-V exception and interrupt handling includes:
- Saving and restoring CPU registers around traps
- Implementing handlers for:
- Supervisor software interrupt
- Supervisor timer interrupt
- Halting the CPU for all other interrupts and exceptions
------
TODOs:
1. add support for registering interrupt handlers via request_irq() and
further adoption of the common IRQ framework.
2. add support for external interrupt.
Tracked-On: #8813
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
