checking the inputs explicitly instead of using Assert.
Tracked-On: #4003
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Shuo Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Guest OS for example Windows will disable bars before shutdown. Bars
are unregistered when they are disabled. Trying to unregister a bar
which has been unregistered causes a assertion. In pci_emul_free_bars
only those enabled bars should be unregistered.
Tracked-On: #2962
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
Sometimes guest OS writes PCIR_COMMAND register to disable the device,
then update the bar address followed by a write to PCIR_COMMAND register
to enable the device again. In this case unregister_bar/register_bar
should be called otherwise the IO/MMIO regions monitored by device model
will not be updated accordingly.
Tracked-On: #2962
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Signed-off-by: Liu Shuo A <shuo.a.liu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
Guest OS (e.g. Linux) may rely on a gap in E820 map in the 32-bit memory
space to determine the MMIO space for its PCI devices. Leave this gap
when building E820 map to keep the guest's PCI subsystem working.
After commit 7752d5cfe3d11ca0bb9c673ec38bd78ba6578f8e, Linux kernel no
longer requires the MMCONFIG region to be reserved in the E820 map.
Nonetheless, keep it in the reserved region to be on the safe side.
Tracked-On: #2843
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
Add the PCI MMIO fallback handler to the 64-bit PCI host aperture, so
that the guest won't inadvertently crash acrn-dm due to unhandled MMIO.
Tracked-On: #2792
Signed-off-by: Peter Fang <peter.fang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
There was a workaround in DM that allocates PCI 64bit mem bar in 32bit mem space
if the bar size is within 32MB.
After the workaround being removed, there is an issue to enter fastboot
mode for inappropriate handling of 64bit mem bar in guest driver.
The patch bring the workaround back, and skip the workaround when the guest
is booted by OVMF.
Revert the patch after the guest fixs the issue of handling 64bit mem bar in
fastboot mode.
Tracked-On: #2677
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
1G PCI hole is added just after 4G address which is used as the
PCI high MMIO address space. Guest high memory is mapped from 5G
address for both EPT and device model user space address. Guest
e820 table and API vm_map_gpa are updated accordingly.
Tracked-On: #2577
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Remove the >32MB limitation for 64bits mmio hole allocation, ACRN
hasn't met such buggy devices for this limitation. Besides, OVMF
has one bug which requires 64bits BAR must allocate from 4G+ address,
otherwise trigger assert. This patch can workaround it.
Tracked-On: #2577
Signed-off-by: Liu Shuo A <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Limit 64 bits PCI BAR space from 0x100000000UL ~ 0x140000000UL,
as HV now only support 0x400000000UL+0x80000000 as top of guest memory
address. EPT table size is static allocated.
Tracked-On: #2577
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The patch fix some string operations issues and also improve readability
of several snippet.
Tracked-On: #2133
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
Replace sscanf in device model hw directory
Tracked-On: #2079
Signed-off-by: Long Liu <long.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: <yonghua.huang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Always enforce data size when using BAR access functions.
Currently, the size serves as a hint to the BAR access functions and
these functions are expected to behave accordingly. Some of the access
functions, e.g. virtio ones, don't always truncate the data but expect
the caller to take care of the data size. This causes problems with
OVMF's virtio drivers during I/O instruction emulation because RAX can
contain junk bits that shouldn't be written to the device.
v1 -> v2:
- improve readability
Tracked-On: #1935
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
It is preferred to state the absence of a return value explicitly in the
doxygen-stile comments. Currently there are different styles of doing this,
including:
@return None
@return NULL
@return void
@return N/A
This patch unifies the above with `@return None`.
Tracked-On: #1595
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
According to PCI spec 3.0 section 6.2.2 "Device Control", guest
could write the command register to control device response to
io/mem access.
The origial code register/unregister the memory range which is
not suitable because it can't handle the sequence:
1. disble the device response to specific memory range
2. reboot guest (DM will try to free the memory range which
was freed in step 1 already)
Tracked-On: #1277
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Remove the workaround and will submit the fixing patch.
Tracked-On: #1277
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This is temperory workaround for DM crash when doing fastboot
reboot. In fastboot, it will disable USB host functionality by
disable device respsone to one PCI bar. While DM code just release
the bar in this case. Which break the reboot functionality.
The workaround is to remove the assert to avoid DM abort. This is
safe because reboot will remove all memory range registered.
We will have offiical fixing later.
Tracked-On: #1277
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
if some pci devices behind gvt got failures when initlizing at init_pci(), gvt
instance have no chance to be destroied even acrn-dm exits.
NOTE: this patch can not work standalone, a following patch to kernel
side(643d40961cf: "vhm: init client->kthread_exit true") is requied as well,
otherwise it will stucks during destroying gvt instance.
Tracked-On: #1141
Signed-off-by: Li Zhijian <zhijianli88@163.com>
This function add high level reset_vdev function. Which is
implemented to call deinit/init pairing to emulate the virtual
device reset operation.
This patch also add the system reset which keep the UOS RAM
content functionality to DM.
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
- hardcode the devices' GSI info based on the platform
- reject the passthrough if the following requirement is not met
all the PCI devices that are sharing the same GSI should be assigned
to same VM to avoid physical GSI sharing between multiple VMs.
v4 -> v5
* Move the gsi_dev_mapping_tables definition in a separate file
* Add the GSI info that might be used by GPIO
* Update the HW name
v3 - > v4
* Refine the format of raw data to improve the readability
* Remove the redundant code when adding the new dev into the gsi
sharing group
v2 -> v3
* Add the MSI/MSI-x capability check
Do not add the device which supports MSI/MSI-x to the GSI sharing
group.
v1 -> v2
* Update the GSI raw data based on SBL
* Free the resources when gsi sharing violation occurs
* Move the MACRO PCI_BDF(b, d, f) to pci_core.h since passthrough.c
and gsi_sharing.c are both using it
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Edwin Zhai <edwin.zhai@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
To enable GPU passthru, BAR2 allocation had problems when the allocation
is above the 4GB memory.This change is to accomodate the 256MB aperture
allocation in BAR2 to a more managable address.
v2: changed the MEMBASE64 address instead of increasing the mem_size.
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Gong Zhipeng <zhipeng.gong@intel.com>
acrn-dm runs to segmentation fault when failed to create VMs with
improper parameters.
If vdevs failed to be created, they are still be freed in deinit(),
and dereference the null pointers leads to segfault.
Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Virtio 1.0 introduced several PCIY_VENDOR capabilities. When trying to
write to these capabilities no action is taken so the registers in
the capability of VIRTIO_PCI_CAP_PCI_CFG such as bar, offset and length
remain the default value 0. Later a read or write of pci_cfg_data needs
these information to perform the indirect read or write to the bar
region.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
pci_emul_find_capability can be used to get the offset of a PCI
capability in PCI configuration space.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
suspicious dereference of pointer 'fi->fi_devi'
by passing it to function 'pci_emul_free_bars()'
before NULL check.
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is reported to cause UOS reboot fail becasue the
pci_businfo[] only be allocated when calling pci_parse_slot
in dm initialization while UOS reboot will not allocate again.
So we can't free it here.
This reverts commit 7aaff68798.
Signed-off-by: Jie Deng <jie.deng@intel.com>
Entries of pci_businfo[] allocated in function "pci_parse_slot"
using calloc need to be freed when deinit.
Signed-off-by: Jie Deng <jie.deng@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
The original code assume there is only one configuration for
virtio-blk, and 'b' is just located after that configuration,
so to get the value of 'b', it will end char *config by adding
'\0' after the first configuration.
Thus, char *config will change from:
/XXXX_vdisk_file,range=xxx/xxx
to:
/XXXX_vdisk_file
and char *b will point to:
range=xxx/xxx
So, the range will never take effect for virtio-blk.
Now, 'b' is designed to located just after emul, and
char *config will point to all configurations after 'b'.
Note: only ",b," is taken for boot device option.
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Two memory ranges are allocated:
- PCI ECFG
- PCI hole
They should be released when deinit_pci. Old code mark
this two ranges not unregistered. Which is wrong for
warm reboot case. Make them could be unregistered.
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
We didn't release mmio/io data structure related with PCI bar
of pci dev. Which could trigger memory leak when reboot UOS.
With the new patch, we release the mmio/io data structure
when pci core tries to deinit pci device.
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
pci_emul_add_capability is needed by virtio 1.0 framework to add
pci vendor capability from outside of pci core.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Now, we could use option:
-s 3,virtio-blk,/XXXX_vdisk_file,b
to show this virtio device is boot device for guest.
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Writing PCIR_BIOS is to get PCI ROM resource length. Ingore the request
as it's not support currently. Else, guest might get wrong information
about the PCI ROM resource.
Signed-off-by: Shuo Liu <shuo.a.liu@intel.com>
