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release_1.6
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3 Commits

Author SHA1 Message Date
Li Fei1
4b6dd19ad1 hv: pci: rename CFG read/write function for PCI-compatible Configuration Mechanism 
Move CFG read/write function for PCI-compatible Configuration Mechanism from
debug/uartuart16550.c to hw/pci.c and rename CFG read/write function for
PCI-compatible Configuration Mechanism to pci_pio_read/write_cfg to align with
CFG read/write function pci_mmcfg_read/write_cfg for PCI Express Enhanced
Configuration Access Mechanism.

Tracked-On: 
Signed-off-by: Li Fei1 <fei1.li@intel.com>
 2020-03-12 09:17:02 +08:00
Li Fei1
1e50ec8899 hv: pci: use ECAM to access PCIe Configuration Space 
Use Enhanced Configuration Access Mechanism (MMIO) instead of PCI-compatible
Configuration Mechanism (IO port) to access  PCIe Configuration Space
PCI-compatible Configuration Mechanism (IO port) access is used for UART in
debug version.

Tracked-On: 
Signed-off-by: Li Fei1 <fei1.li@intel.com>
 2020-01-07 16:05:30 +08:00
Li, Fei1
cc47dbe769 hv: uart: enable early boot uart 
Enable uart as early as possible to make things easier for debugging.
After this we could use printf to output information to the uart. As for
pr_xxx APIs, they start to work when init_logmsg is called.

Tracked-On: 
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
 2019-07-26 09:10:06 +08:00