Commit Graph

6 Commits

Author SHA1 Message Date
Li Fei1
04a104e856 hv: page: use dynamic page allocation for pagetable mapping
For FuSa's case, we remove all dynamic memory allocation use in ACRN HV. Instead,
we use static memory allocation or embedded data structure. For pagetable page,
we prefer to use an index (hva for MMU, gpa for EPT) to get a page from a special
page pool. The special page pool should be big enougn for each possible index.
This is not a big problem when we don't support 64 bits MMIO. Without 64 bits MMIO
support, we could use the index to search addrss not larger than DRAM_SIZE + 4G.

However, if ACRN plan to support 64 bits MMIO in SOS, we could not use the static
memory alocation any more. This is because there's a very huge hole between the
top DRAM address and the bottom 64 bits MMIO address. We could not reserve such
many pages for pagetable mapping as the CPU physical address bits may very large.

This patch will use dynamic page allocation for pagetable mapping. We also need
reserve a big enough page pool at first. For HV MMU, we don't use 4K granularity
page table mapping, we need reserve PML4, PDPT and PD pages according the maximum
physical address space (PPT va and pa are identical mapping); For each VM EPT,
we reserve PML4, PDPT and PD pages according to the maximum physical address space
too, (the EPT address sapce can't beyond the physical address space), and we reserve
PT pages by real use cases of DRAM, low MMIO and high MMIO.

Signed-off-by: Li Fei1 <fei1.li@intel.com>
Tracked-On: #5788
2021-03-11 12:36:17 +08:00
Yonghua Huang
f7842878ae config-tool: refine software SRAM config of pre-RTVM
- Define 'PRE_RTVM_SW_SRAM_ENABLED' only if both
     prelaunch RTVM and Software SRAM are configured in
     current scenario.

   - Define 'PRE_RTVM_SW_SRAM_BASE_GPA' and
     'PRE_RTVM_SW_SRAM_END_GPA' only if
     'PRE_RTVM_SW_SRAM_ENABLED' is defined.

Tracked-On: #5649
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2021-02-25 13:21:41 +08:00
Yang,Yu-chu
0c7d8dd8cc config-tools: check vmsix enablement for ehl-crb-b
Assign extra vbar for vmsix devive for ehl-crb-b only.

Tracked-On: #5693
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-02-03 13:53:18 +08:00
Xie, nanlin
0b6840d1be acrn-config: Update generated configuration source code
1.Reorg generated configuration source code structure
2.Upstream generated configuration source code based on generic board infomation
3.Update license date from 2020 to 2021

Tracked-On: #5644
Signed-off-by: Xie, nanlin <nanlin.xie@intel.com>
2021-02-02 16:53:56 +08:00
Junjie Mao
daf495bfc8 config_tools/target: generate Software SRAM related info
This patch parsees physical RTCT entries and dump information about pseudo
RAM into the board XML files. A macro named PRE_RTVM_SW_SRAM_BASE_GPA is
added to the generated misc_cfg.h according to recent design changes.

This patch still writes the board XML file manually, following the
convention of the current framework. Using XML-based approach requires a
complete refinement of the current generation process as the root
`acrn-config` node has its own text among adjacent children.

Tracked-On: #5649
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-01-27 16:39:24 +08:00
Xie, nanlin
97c9b24030 acrn-config: Reorg config tool folder
Remove vm_configs folder and move all the XML files and generic code example into config_tools/data

Tracked-On: #5644
Signed-off-by: Xie, nanlin <nanlin.xie@intel.com>
2021-01-27 11:08:28 +08:00