2 Commits

Author	SHA1	Message	Date
Yonghua Huang	9e8c1a1508	hv: reset CAT Capacity Bitmask(CBM) MSRs ... ACRN get messy default values for some CAT CBM MSRs, these unexpected default value will result in TCC Software SRAM initializes crash. This patch resets above error default values before calling CRL(cache reserve library) ABI initializaion function. Tracked-On: #6780 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>	2021-11-12 16:25:35 +08:00
Liang Yi	688a41c290	hv: mod: do not use explicit arch name when including headers ... Instead of "#include <x86/foo.h>", use "#include <asm/foo.h>". In other words, we are adopting the same practice in Linux kernel. Tracked-On: #5920 Signed-off-by: Liang Yi <yi.liang@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>	2021-05-08 11:15:46 +08:00