Support shared memory based inter-vm communication for ACRN
post-launched VMs. The ivshmem mediator emulates one standard
PCI device which expose the shared memory region through its BAR2.
The shared memory region is allocated through Linux shm mechanism and
post-launched VM needs to specify the shm name and size as the acrn-dm
parameter, the VMs have same shm name parameter can communicate over
the shared memory.
For first stage, only support shared memory. Consider to support
notification(interrupt) in future.
To add a ivshmem device in device model, the usage as below
-s N,ivshmem,shm_name,shm_size
v2: Implement the ivshmem MMIO registers emulation
v3: Refine code style
Add ivshmem device usage
Refine MMIO register return value
v4: Refine comments
Use logger interfaces to print logs
Tracked-On: #4853
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Currently the class type of igd_lpc bridge PCI device is not initialized.
In such case the guest driver doesn't detect the platform correctly when it
is in GVT-d mode. Then the linux i915 driver can't work.
Tracked-On: #4745
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Currently the DM will return the passthrough device to SOS when the DM
needs to be terminated. But the device is not reset. In such case it
will cause the garbage display issue when the GPU passthrough device
is returned.
Tracked-On: #4719
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
EHL graphics data stolen memory(DSM) info has diff with KBL/WHL,
which includes two parts:
(1) DSM register location in pci config: on KBL/WHL, the register
locates on 0X5C, while on EHL, the register locates on 0xC0.
(2) DSM address length: On KBL/WHL,
DSM addr has 32 bits, while on EHL,DSM addr has 64 bits.
Here, refine graphics data stolen memory passthru to enable GVT-d on EHL platforms.
v3 -> v4:
* add MICRO INTEL_ELKHARTLAKE
v2 -> v3:
* refine discription,MICRO name
* refine code style
v1 -> v2:
* add callback functions for scalability
Tracked-On: projectacrn#4700
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
previous patch fails to align SUBVID, SUBDID of igd-lpc with physical one.
this patch corrects the errors and refine the code.
Tracked-On: #4405
Signed-off-by: Junming Liu <junming.liu@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
There're some PCI devices need special handler for vendor-specical feature or
capability CFG access. The Intel GPU is one of them. In order to keep the ACRN-HV
clean, we want to throw the qurik part of PCI CFG asccess to DM to handle.
To achieve this, we implement per-device policy base on whether it needs quirk handler
for a VM: each device could configure as "quirk pass through device" or not. For a
"quirk pass through device", we will handle the general part in HV and the quirk part
in DM. For a non "quirk pass through device", we will handle all the part in HV.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
In order to add GVT-D support, we need pass through stolen memory and opregion memroy
to the post-launched VM. To implement this, we first reserve the GPA for stolen memory
and opregion memory through post-launched VM e820 table. Then we would build EPT mapping
between the GPA and the stolen memory and opregion memory real HPA. The last, we need to
return the GPA to post-launched VM if it wants to read the stolen memory and opregion
memory address and prevent post-launched VM to write the stolen memory and opregion memory
address register for now.
We do the GPA reserve and GPA to HPA EPT mapping in ACRN-DM and the stolen memory and
opregion memory CFG space register access emulation in ACRN-HV.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Let the ACRN HV to do this in shutdown sequence. In this case, the RTVM could be
still alive if something wrong happened to cause the DM died.
Tracked-On: #4428
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Since this callback is only useful for pass through PCIe device and now pass through
PCIe device emulation has splited from DM to HV. we could remove this callback now.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
SOS should not access the physical PCI device which is assigned to other guest.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Now we split passthrough PCI device from DM to HV, we could remove all the passthrough
PCI device unused code.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
In this case, we could handle all the passthrough PCI devices in ACRN hypervisor.
But we still need DM to initialize BAR resources and Intx for passthrough PCI
device for post-launched VM since these informations should been filled into
ACPI tables. So
1. we add a HC vm_assign_pcidev to pass the extra informations to replace the old
vm_assign_ptdev.
2. we saso remove HC vm_set_ptdev_msix_info since it could been setted by the post-launched
VM now same as SOS.
3. remove vm_map_ptdev_mmio call for PTDev in DM since ACRN hypervisor will handle these
BAR access.
4. the most important thing is to trap PCI configure space access for PTDev in HV for
post-launched VM and bypass the virtual PCI device configure space access to DM.
This patch doesn't do the clean work. Will do it in the next patch.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Intel Graphics Device(IGD) passthrough on Windows guest
has the restriction that it need a lpc bridge device
located in 00:1f.0 PCI slot.
This patch add a 'gpu' option for 'passthrou' type device,
which will create the dedicated "igd-lpc" for IGD passthrough.
Tracked-On: #4405
v2 -> v3:
* refine the commit message and comments.
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Wu Binbin <binbin.wu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Intel Graphics Device(IGD) passthrough on Windows guest
has the restriction that it need a lpc bridge device
located in 00:1f.0 PCI slot.
This patch add an extra lpc class for this restriction,
the lpc class will be used to create a dummy lpc bridge.
To enable gvt-d GOP driver work,
the VID, DID, REVID, SUBVID, SUBDID of igd-lpc
need aligned with physical one.
Tracked-On: #4405
v2 -> v3:
* refine the comment message and comments.
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Wu Binbin <binbin.wu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
uos IGD driver need opregion when enable GVT-d.
This patch pass-thru opregion to uos gpu.
Here is the steps:
(1) set opregion gpa(guest physical addrress) 0xDFFFD000;
(2) get opregion hpa(host physical addrress);
(3) build EPT mapping for opregion.
v1 -> v2:
* initialize the EPT mapping for passthrough GPU opregion region
in passthru_init instead of reading the ASLS config space
v2 -> v3:
* add EPT unmap when deinit
* change some micro name
Tracked-On: #4360
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Wu Binbin <binbin.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
gop driver and uos IGD driver will use
graphics stolen memory(gsm) when enable GVT-d.
This patch pass-thru gsm to uos gpu.
After set physical GPU gsm size 64MB in host BIOS:
Here is the steps:
(1) set gsm gpa(guest physical addrress) 0xDB000000;
(2) get gsm hpa(host physical addrress);
(3) build EPT mapping for gsm.
v1 -> v2:
* initialize the EPT mapping for passthrough GPU gsm region
in passthru_init instead of reading the BDSM config space
v2 -> v3:
* add EPT unmap when deinit
* change some micro name
Tracked-On: #4360
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Wu Binbin <binbin.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Now the PCI bar uses the hardcoded prefetch property
for the pass-through device.
This doesn't work when trying to load windows GPU driver
for the pass-through GPU device.
For pass-through devices,
set the bar prefetchable property the same as physical bar.
Tracked-On: #4282
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
When update pci bar addr,
DM may change the bar property by func pci_cfgrw.
PCI spec chapter 'Base Addresses' shows
bits 0~3 are readonly of memeory space BAR,
so this change won't happen.
This patch ensures pci bar property unchanged
when update pci bar addr.
Tracked-On: #4282
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
use acrn-dm logger function instread of perror,
this helps the stability testing log capture.
Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Do reset for passthrough PCI device by default when assigning it to post-launched
VM:
1. modify opt "reset" to "no_reset" -- could enable no_reset for debug only
2. remove "ptdev_no_reset" opt. It could be replaced by setting "no_reset" for
each passthrough device.
Tracked-On: #3465
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Now the GVT already tries to reserve the region.
the problem is that the region should be
reflected in PCI BUS0 memlimit32 and updated to DSDT table.
As the GVT PCI bar0/2 is in reserved region
and not updated to memlimit32 in DSDT table,
the problem is triggered.
Tracked-On: projectacrn#4227
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
The current design has the following problem:
uos kernel may update gvt bars' regions,
but ACRN-DM doesn't know this update.
ACRN-DM only know out-of-date gvt bar regions,
For simplicity, mark these bar regions as OOD bar regions.
uos kernel may allocate OOD bar regions for
other pci devices, which will result in ACRN-DM
bar regions inconsistency with uos kernel.
The new design is the following:
When other pci device update bar regions
(1) ACRN-DM updates gvt bars' regions
provided by a system file.
(2) ACRN-DM updates this pci device bar regions
v5 -> v6:
* add more comments
v4 -> v5:
* remove & for callback func assignment
v3 -> v4:
* compare gpu bar address to avoid unnecessary
* unregistered/registered operation
v2 -> v3:
* call unregister_bar and register_bar when update gvt bars
* update gvt reserved regions when update gvt bars
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
ACRN-DM has reserved gvt bar regions.
This patch ensures other pci devices' bar regions
won't overlap with reserved bar regions.
v6 -> v7:
* rename some struct and func
v5 -> v6:
* remove outdated comment
* add comments for code reading
* code cleaning about gvt bar0 and bar2 size
v4 -> v5:
* rename adjust_bar_region and adjust_bar_region_by_gvt_bars
* change adjust_bar_region_by_gvt_bars interface for code cleaning
v3 -> v4:
* add static struct gvt_region instead of definition or pointer array.
v2 -> v3:
* repalce pci_emul_alloc_bar with gvt_reserve_resource when allocate gvt bars
* use register_bar to detect if gvt bars confilts with pci devices
v1 -> v2:
* don't limit the gvt bar type is MEM32 when deal with pci bar
* add is_two_region_overlap func to detect if two regions overlap
* add region array to store gvt bar0 and bar2 regions
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The current design has the following problem:
gvt uses some pci bar regions,
but ACRN-DM isn't aware of these regions.
So ACRN-DM may allocate these regions for other pci devices,
which will result in other pci devices bar regions
overlap with gvt bar regions.
The new design is the following:
(1) ACRN-DM reads gvt bar regions
which are provided by physical gpu;
(2) ACRN-DM reserves gvt bar regions
v6 -> v7:
* use array to store reserved bar regions
* rename some struct and func
v5 -> v6:
* rename enable_gvt to gvt_enabled
* add a interface to reserve bar regions
* reserve gvt bar regions
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The acrn vhm driver will convert all PCI configure space access to
PCI_CFG type, so the pci_emul_cfgaddr and pci_emul_cfgdata will nerver
be invoked. Remove these useless functions.
Tracked-On: #3999
Signed-off-by: Gao Junhao <junhao.gao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
int snprintf(char *str, size_t size, const char *format, ...)
The functions snprintf() write at most size bytes (including the
terminating null byte('\0')) to str.
only when returned value of snprintf is non-negative and less than size,
the string has been completely written.
Tracked-On: #3789
Signed-off-by: Junhao Gao <junhao.gao@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
After Windows 10, version 1607, the cross-signed drivers are forbiden
to load when secure boot is enabled.
Details please refer to
https://docs.microsoft.com/en-us/windows-hardware/drivers/install/kernel-mode-code-signing-policy--windows-vista-and-later-
That means the kvm-guest-drivers-windows can't work when secure boot enabled.
So we found another windows virtio FE drivers from Oracle to resolve this issue
but have to change another subsystem vendor ID for the virtio BE services.
This patch introduces a new DM CMD line "--windows" to launch WaaG with Oracle virtio devices including
virtio-blk, virtio-net, virtio-input instead Redhat. It can make virtio-blk, virtio-net and virtio-input
devices work when WaaG enabling secure boot.
Tracked-On: #3583
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
This patch is used to support multiple Event Ring Segment Table (ERST).
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This patch only changes some names of varaibles about Event Ring Segement
Table (ERST), and doesn't modify any code logic.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The block count of the struct usb_xfer is hard coded by the macro
USB_MAX_XFER_BLOCKS (1024), it wastes memory if 1024 blocks are
allocated for low speed transfer such as control transfer or interrupt
transfer. This patch introduces a new method to allocate different
number of blocks according to different endpoint type.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The overrun and underrun event are used in the timing control machanism,
this patch is used to implement this feature.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The Block Event Interrupt (BEI) bit in the TRB descriptor could
delay the triggering of interrupt. For most OSes, the native
driver for xHCI will use this bit to optimize the IO performence,
due to reduction of number of interrupts.
But in Linux, the native xHCI driver for Intel brand controller
doesn't use this bit. It is fine for the native scenario due to
most work is completed by hardware. But in virtualization scenario,
it is almost impossible to support heavy data IO such as high
resolution video recording (ISOC transfer).
Hence, this issue is solved by a 'quirk' when the intel hardware is
emulated (when vendor id is set as 0x8086). For other cases, a
virtal hardware called 'ACRN xHCI' is emulated, and both Linux and
Windows will use BEI bit by default.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The old logic to emulate MFINDEX register is not right, this patch
is used to fix it.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Just changed the name of the variable and didn't change any emulation
code logic.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
In the struct usb_block, there are some fields such as 'ccs',
'streamid', which should not be seen in the USB layer. This
patch intruduces new struct xhci_block to include the variables
for xHCI emulation.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
When control transfer is detected and an unnecessary reset of
struct usb_xfer is conducted. This behavior is not necessary
and this patch is used to remove it.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
In the process of USB data transfer, there three kinds of data blocks:
a. Non data block, which contains some control information;
b. Partial data block, which contains part of a large data chunk;
c. Full data block, which contains a complete data chunk.
In previous implementation, the differences mentioned above are described
by the usb_block::chained. But the 'chained' is concept in the xHCI area
and should not appear in the USB layer. This patch introduces enum type
usb_block_type to replace the 'chained' field in struct usb_block.
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Some names of functions and variables are long and not exact, this
patch is used to change them, no logic code are affected. The
changing included:
usb_data_xfer -> usb_xfer
usb_data_xfer_block -> usb_block
usb_xfer_blk_stat -> usb_block_stat
usb_data_xfer_append -> usb_block_append
USB_XFER_BLK_* -> USB_BLOCK_*
Tracked-On: #3628
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Add subclass for virtio-console pci device. Without the subclass, the
device may be probed by 8250_pci serial driver, and lead to segment
fault in acrn-dm. This issue appears when running debian as Guest OS.
But there is a potential issue, if a new serial driver, which use class
and subclass same as virtio-console, the problem may still trigger. Need
to fix it case by case.
Tracked-On: #3615
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
