Move vcpu API create_vcpu to common.
* Break create_vcpu into common vcpu init and arch_init_vcpu
for arch-specific initialization.
* Move vcpu_thread to arch-specific and rename to arch_vcpu_thread
Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This commit moves struct acrn_vm under common header vm.h, and move some
x86-specific members of struct acrn_vm into arch_vm. This commit focuses
on struct cleanup only. API cleanup will be in future patch series.
The affected members are:
e820_entry_num
e820_entries
wire_mode
wbinvd_lock
vlapic_mode_lock
vcpuid_entry_nr
vcpuid_level
vcpuid_xlevel
vcpuid_entries
reset_control
pm
sworld_control
sworld_snapshot
intr_inject_delay_delta
Moved to common vm.h:
ept_lock -> rename to stg2pt_lock
ept_pgtable -> rename to stg2_pgtable
nworld_eptp -> rename to root_stg2ptp
emul_mmio_lock
nr_emul_mmio_regions
emul_mmio
emul_pio
To avoid circular dependency, some in-header helpers are also moved into
common vm.h.
Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This commit cleans up struct acrn_vcpu. vcpu API cleanup will be in
future patch series.
Create a common vcpu.h hosting struct acrn_vcpu, and move some x86
specific members of struct acrn_vcpu into struct acrn_vcpu_arch. These
members includes:
reg_cached
reg_updated
inst_ctxt
And pending_req is being moved from arch to common.
And the maximum number of events (i.e., VCPU_EVENT_NUM) are being
replaced by MAX_VCPU_EVENT_NUM.
To avoid circular dependency, some in-header helpers are moved into
vcpu.c with only prototypes being declared inside header.
Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Add stack protector implementation for RISC-V architecture using a
global __stack_chk_guard variable. This differs from x86 which uses
per-CPU stack canaries.
Tracked-On: #8834
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Stack canary implementation varies across architectures. x86 uses a
per-pCPU __stack_chk_guard while RISC-V uses a global variable shared
across all pCPUs. Move struct stack_canary from the common per_cpu
structure to per_cpu_arch to allow architecture-specific stack
protection implementations.
Tracked-On: #8834
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements relocation support for ACRN RISC-V to enable
position-independent execution. The hypervisor can now be loaded at any
physical address and will automatically relocate itself at runtime. Key
changes:
- Add relocate() function to process R_RISCV_RELATIVE relocations in
.rela sections during early boot
- Implement arch_get_hv_image_delta() to calculate the load address offset
from the configured base address
- Add relocation processing in cpu_entry.S before jumping to C code
- Update linker script to include .rela sections for relocation data
- Define R_RISCV_RELATIVE relocation type and linker symbol definitions
Tracked-On: #8825
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
add BSP and AP initialization function.
and call uart16550_init to update uart_base_address
after init paging.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
this patch calculate riscv static pages number for page pool.
riscv donot need to map guest memory. use link script address
label to map code size.
For risc-v:
1) if the platform doesn't support PCIe devices
The address space layout for risc-v is like
| |
| MMIO |
| |
| ... |
| |
| RAM |
| |
For all its address space, one 1GB page table is enough which cover 512G
For MMIO or RAM, if its start address and end address is 1G aligned, there's no 2M
or 4K page table is needed. if their address are not 1G aligned, two 2M page table
is enough for MMIO or RAM. The issue here is that if we neetid 4K page entries for
different page attributes. So we need to reserve enough 4K page tables for that requirement.
2) if the platform support PCI devices, for the low MMIO range, another two 2MB page
table may needed. for the high MMIO range, its depends on the max physical address bits of
the platform and the high MMIO range reserved by the BIOS.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Add hypervisor pagetable manipulate interface to riscv arch directory,
which is needed by the common interface, and add riscv ppt pgtable
structure implementation.
Tracked-On: #8831
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: hangliu1 <hang1.liu@intel.com>
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
add pgtable callbacks set_pgentry to implement arch specific
set generic page table entry for any paging level, and remove
x86 specific tweak_exe_right/recover_exe_right callbacks, move
the logic in set_pgentry callback.
remove common set_pgentry function to avoid confusing.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
for x86, when using a new page to set up page table,
sanitize to specific hpa page address is needed, however,
for other arch, sanitized to 0 is fine. To avoid duplicate memory
setting at the time of alloc_page and sanitize pte, replace
memset in alloc_page with sanitized pte operation.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
move early_pgtable_map_uart and pgtable_create_trusty_root
to x86 code, and provide calling with x86 private header
pagemisc.h
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
this patch moves function xx_offset and xx_index to common code,
Add arch interface arch_quirk/arch_pgtle_page_vaddr and
arch_pgtle_large.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
move _page_table_level to common, and rename functions and
variables to comform with pgtln style
when we refer to pgtl0e, it means the lowest translation
table entry, while the "pte" refers generic page table entry.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
add x86 mm_common.h to map common macro name to x86 name
and chang them in common/mmu.c, replace XX_PFN_MASK with
PFN_MASK, since they are the same.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The sanitized page is used to mitigate l1tf for x86, but sanitized_page_hpa
is the hpa used to set in the page table entry when delete or modify
page happens, it is by default is 0, other arch donot need to init it.
move this part to common for other arch to reuse it.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
move struct pgtable and page_pool to common code and
move alloc_page/free_page/init_page_pool to common
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
move some funcitons like hpa2hva to common file.
change some files to include file from asm/pgtable.h to common/pgtable.h
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
get_vm_from_vmid,is_paused_vm and is_poweroff_vm should be common APIs.
But now doesn't implement them as common for not introduce more VM related
data structure and APIs.
Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The RISC-V calling convention defines a full descending stack, where 'sp'
points to the last used stack address. The current implementation of
cpu_ctx_save() subtracts only CPU_REGS_OFFSET_SCRATCH from 'sp', which
allocates 8 bytes too few and may overwrite the caller's stack contents.
Fix this by adjusting CPU_REGS_OFFSET_LAST to include the last slot,
ensuring the full context save/restore area is properly reserved.
Fixes: 6276763cd (hv: riscv: implement cpu_ctx_save and cpu_ctx_restore)
Tracked-On: #8827
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Use tp register directly for arch_get_pcpu_id. This can eliminate the
unnecessary mv instruction.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
MMIO read/write without memory order should be common ARCH, without
PIO support shouldn't use PIO APIs, so implement them as empty.
Tracked-On: #8807
Signed-off-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
implement arch_cpu_dead and arch_cpu_do_idle for riscv, arch_cpu_dead and
arch_cpu_do_idle will be called by common module.
Tracked-On: #8812
Signed-off-by: Haicheng Li <haicheng.li@outlook.com>
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
cpu_dead calls arch_cpu_dead, cpu_do_idle calls arch_cpu_do_idle,
arch_cpu_dead and arch_cpu_do_idle are required to be implemented by
each architecture.
Tracked-On: #8812
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
move run_idle_thread and default_idle to schedule file as common
function.
Tracked-On: #8812
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
stack_frame is not only for vcpu thread, host thread needs
it, so move stack_frame out of vcpu file.
Tracked-On: #8812
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
delivery mode and idle mode are x86 specific percpu, so move it from common to
x86 arch, also change the name of mode_to_idle to be idle_mode, change the name
of mode_to_kick_pcpu to be kick_pcpu_mode.
Tracked-On: #8812
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
add arch_send_reschedule_request, which is called by make_reschedule_request, for X86
arch_send_reschedule_request will call kick_pcpu, arch_send_reschedule_request is arch
public API, which is needed to be implemented by each architecture.
Tracked-On: #8812
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Convert IRQ-related macros to static inline functions and introduce
wrappers for arch-specific implementations. This follows the style we
defined for multi-arch development.
This is a follow-up update for commit
a7239d126 ("[FIXME] hv: risc-v add denpended implementation in cpu.h").
CPU_IRQ_ENABLE_ON_CONFIG -> local_irq_enable
CPU_IRQ_DISABLE_ON_CONFIG -> local_irq_disable
CPU_INT_ALL_DISABLE -> local_irq_save
CPU_INT_ALL_RESTORE -> local_irq_restore
Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Fix a compilation error that may occur in some environments due to an
inconsistent type cast. The compiler reports a strict-aliasing violation:
acrn-hypervisor/hypervisor/include/arch/riscv/asm/cpu.h:73:18:
error: dereferencing type-punned pointer will break strict-aliasing rules
[-Werror=strict-aliasing]
73 | *(uint32_t *)(x) = val;
| ^~~~~
Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
local_irq_save() is intended to read and clear the SIE bit in
sstatus (disabling interrupts). The current implementation mistakenly
clears all bits in sstatus.
This patch corrects the inline assembly so that only the SIE bit is affected,
ensuring proper interrupt save/disable semantics on RISC-V.
Fixes: a7239d126 ("[FIXME] hv: risc-v add denpended implementation in cpu.h")
Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements interrupt initialization and the basic
exception/interrupt handling flow on RISC-V.
init_interrupt() needs to be invoked during CPU initialization to
set up the trap vector and enable the interrupt.
RISC-V exception and interrupt handling includes:
- Saving and restoring CPU registers around traps
- Implementing handlers for:
- Supervisor software interrupt
- Supervisor timer interrupt
- Halting the CPU for all other interrupts and exceptions
------
TODOs:
1. add support for registering interrupt handlers via request_irq() and
further adoption of the common IRQ framework.
2. add support for external interrupt.
Tracked-On: #8813
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
