Commit Graph

2 Commits

Author SHA1 Message Date
Jian Jun Chen
1dee977429 hv: risc-v: add relocation support
This patch implements relocation support for ACRN RISC-V to enable
position-independent execution. The hypervisor can now be loaded at any
physical address and will automatically relocate itself at runtime. Key
changes:
- Add relocate() function to process R_RISCV_RELATIVE relocations in
  .rela sections during early boot
- Implement arch_get_hv_image_delta() to calculate the load address offset
  from the configured base address
- Add relocation processing in cpu_entry.S before jumping to C code
- Update linker script to include .rela sections for relocation data
- Define R_RISCV_RELATIVE relocation type and linker symbol definitions

Tracked-On: #8825
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-10-22 10:15:01 +08:00
Jian Jun Chen
6f97ad9fc9 hv: risc-v: add assembly code for BSP and AP boot
The following tasks are done for both BSP and APs:
- Mask all interrupts
- Disable FPU
- Setup stack
- Jump to the C entry of BSP/AP initialization

Additionally, clear BSS sections during BSP boot before
jumping to the C entry point.

Tracked-On: #8788
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Haicheng Li <haicheng.li@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-09-15 13:12:21 +08:00