2 Commits

Author	SHA1	Message	Date
Shiqing Gao	9d95a6adb6	hv: riscv: fix stack allocation in cpu_ctx_save/cpu_ctx_restore ... The RISC-V calling convention defines a full descending stack, where 'sp' points to the last used stack address. The current implementation of cpu_ctx_save() subtracts only CPU_REGS_OFFSET_SCRATCH from 'sp', which allocates 8 bytes too few and may overwrite the caller's stack contents. Fix this by adjusting CPU_REGS_OFFSET_LAST to include the last slot, ensuring the full context save/restore area is properly reserved. Fixes: 6276763cd (hv: riscv: implement cpu_ctx_save and cpu_ctx_restore) Tracked-On: #8827 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-10-14 09:45:17 +08:00
Haicheng Li	6276763cd5	hv: riscv: implement cpu_ctx_save and cpu_ctx_restore ... Implement cpu_ctx_save and cpu_ctx_restore to save and restore CPU registers around exception and interrupt handling on RISC-V. Tracked-On: #8813 Signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: Shiqing Gao <shiqing.gao@intel.com> Signed-off-by: Yifan Liu <yifan1.liu@intel.com> Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-29 14:01:00 +08:00