Enable acrnlog (memory logging) in release builds, default log level
is still controlled by DEBUG_OPTIONS/MEM_LOGLEVEL in scenario file.
Tracked-On: #8805
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Make acrntrace a common feature in both debug and release builds,
instead of debug-only. A new config option ACRNTRACE_ENABLED is added
in scenario to toggle this feature and it is enabled by default.
TRACE_6C is removed due to it violates "C-FN-20: Each function shall
have at most 6 parameters" coding rule and it is never used.
Tracked-On: #8805
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
This patch adds the basic logics to bring up all APs in the C
entry of BSP boot. The mapping between logcial CPU IDs and physical
hart IDs is setup based on the pre-generated data from config tool
by parsing the device tree. Logical CPU ID BSP_CPU_ID will always
map to the BSP hart ID. The per pCPU logic ID is saved in tp register.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Extension Zihintpause (Pause hint) is mandatory for RVA23. asm_pause
is implemented based on "pause" instruction.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Use tp register to hold the current logical CPU ID. This follows the
same design as x86 which uses MSR_IA32_SYSENTER_CS for the same purpose.
riscv uses SBI HSM to start the APs.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The following pcpu related interfaces are moved into common:
- common/cpu.c::start_pcpus
- include/common/cpu.h::get_pcpu_id
- include/common/cpu.h::set_current_pcpu_id
Their arch specific implementations are moved into arch/$(ARCH):
- arch/$(ARCH)/cpu.c::arch_start_pcpu
- include/arch/$(ARCH)/asm/cpu.h::arch_get_pcpu_id
- include/arch/$(ARCH)/asm/cpu.h::arch_set_current_pcpu_id
The following interface is moved into common:
- pcpu_set_current_state (from arch/x86/cpu.c -> common/cpu.c)
The following MACROs are moved into include/common/cpu.h:
- CPU_UP_TIMEOUT
- CPU_DOWN_TIMEOUT
- BSP_CPU_ID
- INVALID_CPU_ID
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Extract common interface to include/lib/bits.h, and invoke the variant
implementation of arch.
Re-implement unlocked functions as C in common library.
Rename bitmap*lock() to bitmap*(), bitmap*nolock() to bitmap*non_atomic().
Tracked-On: #8803
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
extract common barrier interface to include/lib/barrier.h,
and invoke the variant implementation of arch.
Tracked-On: #8803
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
spinlock invokes CPU_INT_ALL_DISABLE & CPU_INT_ALL_RESTOE, bitops
invokes BITS_PER_LONG, add them to pass the build.
current implementation is macro, same as X86. later official mult-arch
change should refactor to static inline on both x86 and risc-v.
Tracked-On: #8803
Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Extract common interface to include/lib/spinlock.h, and invoke the
variant implementation of arch.
Refine assemble macro code in case that ASSEMBLER defined.
Tracked-On: #8803
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Move phys_cpu_num and pcpu_active_bitmap to common, which could be
only accessed by interfaces provided by smp.h.
v2->v3:
1. move ALL_CPUS_MASK/AP_MASK to common cpu.h
v1->v2:
1. preserve phys_cpu_num in x86 but implement arch_get_num_available_cpus()
to provide interface for common code to access.
2. change function name test_xx to check_xx
Tracked-On: #8801
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Move x86 architecture dependent per cpu data into a
seperate structure and embeded it in per_cpu_region.
caller could access architecture dependent member by
using prefix 'arch.'.
v2->v3:
move whose_iwkey, profiling_info and tsc_suspend to x86
v1->v2:
rebased on latest repo
Tracked-On: #8801
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Reviewed-by: Chen, Jian Jun<jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Since there is no common IPI abstraction, the arch_ prefix is redundant.
This patch renames the functions as follows:
- arch_send_dest_ipi_mask -> send_dest_ipi_mask
- arch_send_single_ipi -> send_single_ipi
Tracked-On: #8799
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
This patch implements risc-v specific timer codes. Basically,
risc-v adapts to acrn timer framework with some specific
behaviors. So far, it enables sstc support in h-mode.
Tracked-On: #8792
Signed-off-by: Haicheng Li <haicheng.li@outlook.com>
Co-developed-by: Yong Li <yong.li@intel.com>
Signed-off-by: Yong Li <yong.li@intel.com>
Co-developed-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
For arch specific codes, we use arch_xxx() to name the function.
So, rename cpu_ticks/cpu_tickrate/set_hw_timeout/init_hw_timer
to follow this convention. Then, use arch interface to set timeout
value in update_physical_timer().
Furthermore, remove hw_timer.h and move its contents into common/
timer.h.
Tracked-On: #8792
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch provides dummy implementations of functions and data
structures required for the IPI and SMP call on RISC-V.
It serves as a placeholder to ensure RISC-V builds pass and
is not needed for the final merge.
Official implementations are still WIP by other engineers:
- To be provided in the library patchset (by Haoyu):
uint16_t ffs64(uint64_t value);
bool bitmap_test(uint16_t nr, const volatile uint64_t *addr);
void bitmap_clear_lock(uint16_t nr_arg, volatile uint64_t *addr);
void bitmap_clear_nolock(uint16_t nr_arg, volatile uint64_t *addr);
uint64_t atomic_cmpxchg64(volatile uint64_t *ptr, uint64_t old, uint64_t new);
- To be provided in the platform initialization patchset (by Hang):
void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
bool is_pcpu_active(uint16_t pcpu_id);
uint16_t get_pcpu_id(void);
----------
Changelog:
* Split per_cpu.h implementation into a separate commit.
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Since smpcall depends on the per_cpu_region data structure to access
smp_call_info_data, this patch adds the initial version of per_cpu
support on RISC-V. For now it only includes SMP call related info.
Further refinement will be done in the platform initialization patchset
(by Hang).
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch:
- abstracts the common logic from existing x86 implementation
- moves x86-specific logic to arch/x86/notify.c
A new common/notify.{c,h} is introduced to provide a common SMP call framework for
multi-arch support in ACRN.
arch-specific files such as arch/{x86,riscv}/notify.c is aim to provide the
corresponding implementations respectively.
The framework provides the following common APIs:
- init_smp_call(): initialize the SMP call support during pCPU initialization
- handle_smp_call(): execute the SMP call notification handler
- smp_call_function(): trigger the SMP call request to target pCPUs
Other SW modules should invoke these common APIs to perform arch-independent
SMP operations.
Two arch-specific hooks are abstracted:
- arch_smp_call_kick_pcpu():
- On x86, special handling is required when LAPIC is passthrough.
- On RISC-V, a plain IPI is sufficient to kick the target pCPU.
- arch_init_smp_call():
- On x86, CPU initialization reserves dedicated vectors and
registers callback handlers for purposes such as notifications
or posted interrupts.
- On RISC-V, no special handling is required at present; this
can be extended in the future if needed.
----------
Changelog:
* Merged the following two patches into one:
[RFC PATCH v2 4/7] hv: introduce common/smp.{c,h}
[RFC PATCH v2 5/7] hv: smpcall: x86: adapt to common SMP call
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Rename send_single_ipi() and send_dest_ipi_mask() to
arch_send_single_ipi() and arch_send_dest_ipi_mask() in x86, to make the
naming consistent with the RISC-V implementation and reflect that these
functions are arch-specific.
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Align the prototype of send_dest_ipi_mask() on x86 with the RISC-V
definition. dest_mask is updated from uint32_t to uint64_t:
From: void send_dest_ipi_mask(uint32_t dest_mask, uint32_t vector)
To: void send_dest_ipi_mask(uint64_t dest_mask, uint32_t vector)
On RISC-V, send_dest_ipi_mask() is implemented using SBI interfaces,
where the dest_mask is defined as "unsigned long" in the SBI spec.
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements the IPI for RISC-V using SBI interface.
There is no common IPI concept abstracted, due to the following reasons:
- RISC-V:
Software delivers an IPI to target CPUs via software interrupts.
The interrupt number is fixed for each privilege mode (e.g.,
Supervisor Software Interrupt = IRQ 1, Machine Software Interrupt = IRQ 3).
The actual purpose of the IPI is indicated by an IPI message type,
which is a software-level concept. When the IPI is received,
the target CPU must check the message type to determine the required action.
- x86:
Software delivers an IPI to target CPUs using a specific vector number.
During CPU initialization, software can assign dedicated vectors for
particular purposes. When the IPI is received, the target CPU could
directly invoke the handler bound to that vector.
Each architecture provides its own IPI implementation, and other SW modules
directly call these arch-specific functions.
------
Notes:
* To ensure RISC-V builds pass, an empty `include/arch/riscv/asm/cpu.h`
is added since `debug/logmsg.h` includes `asm/cpu.h`.
* Implemented IPI functionality using the SBI IPI Extension (EID #0x735049).
Legacy SBI extensions are not supported in ACRN.
----------
Changelog:
* Updated commit message and code comments to state explicitly that
legacy SBI extensions are not supported in ACRN.
* Refined the prototype of sbi_send_ipi() to align with the SBI spec:
From: int64_t sbi_send_ipi(uint64_t mask)
To: int64_t sbi_send_ipi(uint64_t mask, uint64_t mask_base)
In ACRN it is invoked as sbi_send_ipi(dest_mask, 0UL), with mask_base
set to 0UL.
* Renamed send_single_ipi() and send_dest_ipi_mask() to
arch_send_single_ipi() and arch_send_dest_ipi_mask() respectively.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements the common SBI interfaces, including
sbi_ecall(), common macros and data structures.
Changelog:
* Renamed SBI_EXPERIMENTAL_x and SBI_VENDOR_x.
* Added description for sbi_ecall().
* Renamed SBI-related enums, macros, and data structures to align with
the SBI specification.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The hypervisor image size is determined at link time, but now it is
calculated and stored in a global variable during mmu initialization,
and the helper function reads from that variable. Change to calculate
it inside helper function to avoid inconsistency.
Tracked-On: #8738
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
The VM-exit instruction length(VMX_EXIT_INSTR_LEN) in VMCS is undefined
on EPT violation, except during delivery of a software interrupt,
privileged software exception, or software exception[1]. Although CPU
is likely to set the field, it can be incorrect in certain cases, such
as cmp+jcc and test+jcc.
Since hypervisor does not know exactly how much bytes needed, and GVA
translation is costly, it first copies at most 15 (VIE_INST_SIZE) bytes
within the page, then decodes the instruction. If more bytes are needed
during decoding and copied length is less than 15, it copies remaining
bytes.
[1] 29.2.5, https://cdrdv2-public.intel.com/671200/325462-sdm-vol-1-2abcd-3abcd.pdf
Tracked-On: #8756
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
In current code process, hyperv data in struct vm_arch is never cleared
during VM shutdown and is retained to next VM launch. As the enabled
bit of hypercall_page msr is not clear, hypercall page might cause fatal
error such as Windows VM BSOD during VM restart and memory
remapping. Hyperv page destory function can ensure hyperv page is
destory during each VM shutdown so hyperv related config such as
hypercall page is established correctly during each VM launch.
Tracked-On: #8755
Signed-off-by: Yichong Tang <yichong.tang@intel.com>
Add reset_control in acrn_vm. Use this reset_control to simulate
RESET_CONTROL(0xCF9) register in hypervisor.
Tracked-On: #8724
Signed-off-by: Yuan Lu <yuan.y.lu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Service VM may write 0x6 to port 0xcf9 to trigger a warm reset, but
current hypervisor always performs a cold reset by writing 0xE to CF9.
Hypervisor should reboot the system in the same mode as Service VM
specified. Specific OS features (like linux pstore) requires warm
reset to keep data across reboot.
The behavior of hv console's reboot command (cold reset) remains
unchanged.
Tracked-On: #8539
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Per SDM, VPDPBUSD/VPDPBUSDS/VPDPWSSD/VPDPWSSDS instructions depend on
CPUID Feature Flag 'AVX-VNNI, AVX512_VNNI, AVX512VL'. 'AVX512_VNNI' and
'AVX512VL' are already exposed to any VM.
'AVX-VNNI' is in CPUID.(EAX=07H,ECX=1):EAX.AVX-VNNI[bit 4]. This patch
is to expose all the CPUID.EAX=07H subleaf features to VMs.
Mask corresponding bits if want to disable some features in the future.
Tracked-On: #8710
Reviewed-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
GAI Tooling Notice: These contents may have been developed with support from one
or more generative artificial intelligence solutions.
This patch is to add doxygen style comments for some elements in
vp-dm_vperipheral vuart module.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
GAI Tooling Notice: These contents may have been developed with support from one
or more generative artificial intelligence solutions.
This patch is to add doxygen style comments for some elements in vp-dm_vperipheral
vrtc module.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
Determine the size of drhd_dev_scope based on DRHD_MAX_DEVSCOPE_COUNT
in board file instead of hardcoding. The current default value 16 will
be used if it is not defined in board file to keep compatibility, a
warning will be raised in this case.
Tracked-On: #8494
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
