8 Commits

Author	SHA1	Message	Date
Haicheng Li	bb9817b866	hv: multi-arch add RISC-V bits library implementation ... Follow multi-arch design, implement the mandatory arch bit ops functions declared in common bits.h for risc-v support. Tracked-On: #8803 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-22 10:52:06 +08:00
Haicheng Li	090aaf4c34	hv: multi-arch add RISC-V barrier library implementation ... Follow multi-arch design, implement the mandatory arch barrier functions declared in common barrier.h for risc-v support. Tracked-On: #8803 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Co-developed-by: Haoyu Tang <haoyu.tang@intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-22 10:52:06 +08:00
Haicheng Li	47944d975d	hv: multi-arch add RISC-V atomic library implementation ... Follow multi-arch design, implement the mandatory arch atomic functions declared in common atomic.h for risc-v support. Tracked-On: #8803 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Co-developed-by: Haoyu Tang <haoyu.tang@intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-22 10:52:06 +08:00
Haicheng Li	d22e21f484	hv: multi-arch add RISC-V spinlock library implementation ... Follow multi-arch design, implement the mandatory arch spinlock functions declared in common spinlock.h for risc-v support. Tracked-On: #8803 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-22 10:52:06 +08:00
hangliu1	0cd5567140	hv:multiarch:riscv: add dummy function ... add dummy function bitmap_set_lock, need to be replaced with real implementation. Tracked-On: #8801 Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Wang, Yu1 <yu1.wang@intel.com> Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-19 15:04:55 +08:00
hangliu1	286c383b53	hv: multiarch: riscv: add dummy header for riscv ... add dummy headrer file for early compile, should be replaced totally later. Tracked-On: #8801 Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Wang, Yu1 <yu1.wang@intel.com> Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-19 15:04:55 +08:00
Haicheng Li	d074ce85eb	hv: multi-arch add RISC-V memory library ... RISC-V use common memory library. Tracked-On: #8794 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Co-developed-by: Haoyu Tang <haoyu.tang@intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-15 14:07:58 +08:00
Shiqing Gao	b0a4c2d024	[FIXME] hv: smpcall: riscv: add placeholder implementations for dependent code ... This patch provides dummy implementations of functions and data structures required for the IPI and SMP call on RISC-V. It serves as a placeholder to ensure RISC-V builds pass and is not needed for the final merge. Official implementations are still WIP by other engineers: - To be provided in the library patchset (by Haoyu): uint16_t ffs64(uint64_t value); bool bitmap_test(uint16_t nr, const volatile uint64_t *addr); void bitmap_clear_lock(uint16_t nr_arg, volatile uint64_t *addr); void bitmap_clear_nolock(uint16_t nr_arg, volatile uint64_t *addr); uint64_t atomic_cmpxchg64(volatile uint64_t *ptr, uint64_t old, uint64_t new); - To be provided in the platform initialization patchset (by Hang): void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync); bool is_pcpu_active(uint16_t pcpu_id); uint16_t get_pcpu_id(void); ---------- Changelog: * Split per_cpu.h implementation into a separate commit. Tracked-On: #8786 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-09 16:37:04 +08:00