Since msr_index relys on the MSR_IA32_L2_QOS_MASKn(n:max to 3)
macro which defined in hv source code, generate array that CLOS number
more than 4 means need define more than 4 macro.
This patch solve such issue by using MSR_IA32_L2/L3_MASK_BASE with the
msr index offset.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The value of CONFIG_MAX_PCPU_NUM is stands for Processor CPU number and
it is grabed from board information.
Tracked-On: #3798
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.the script will parse the the board information which already
generated, $(scenario).xml modified by user, generate scenario
vm configuration and apply to the acrn-hypervisor source code base.
2.parse cpu/memory/ttys/rootfs information from native os and store it to
the source code
3.implemnt scenario_config and it's usage
usage: scenario_cfg_gen.py --board <board_info_file> -scenario <scenario_info_file>
board_info_file : file name of the board info
scenario_info_file : file name of the scenario info
sample:
$ python3 scenario_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
Also improvement board config generate usage:
sample:
$ python3 board_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
V1-V2:
1). parse board_setting.xml was removed as these configuration will be
stitch into scenario configuration
2). parse console for different formats
3). parse epc sections
4). add logical partition rootfs
5). support to parse clos, while webui set to None type
6). support to parse bootargs, while webui set to nul
7). convert '-' to '_' for pci sub class name while generating source file
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
