Commit Graph

12 Commits

Author SHA1 Message Date
Minggui Cao
ac5da17e52 enable rdtscp instruction for guest OS all vCPUs
before just AP can run "rdtscp" intruction, if run it on BSP,
it will cause "illegal instruction"; now align BSP & AP.
also remove duplicated code.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-05-15 17:25:55 +08:00
Yonghua Huang
3c119e124a check validity of 'VM-exit Int-Info' before extracting vector
1. exception vector and other information
   can be extracted from 'VM-Exit Interrupt-Information'
   field of VMCS only if bit31 (Valid) is set.
   -Intel SDM 24.9.2, Vol3

2.  Rename 'exit-interrupt_info' to 'idt_vectoring_info'
    in 'struct vcpu_arch', which is consistent with
    SDM 24.9.3, Vol3

3. 'IDT-vectoring information' in VMCS is 32bit
    -Intel SDM 24.9.3, Vol3

    Update the type of 'idt_vectoring_info' in
    'struct vcpu_arch'from 'uint32_t' to 'uint64_t'.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:55 +08:00
Yonghua Huang
bb011a4316 rename vmexit handlers
this patch is to align the suffix of the handlers' name.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:55 +08:00
Minggui Cao
72b2cb1fa7 remove deadcode of rdtsc_handler/rdtscp_handler
Guest OS rdtsc/rdtscp doesn't trap into hypervisor, so remove them.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:27 +08:00
Qi Yadong
ef0c5ec2e3 hv: cache tsc_offset
Guest write tsc: cache the offset into run_context.tsc_offset;
Guest read tsc : use run_context.tsc_offset to calculate guest_tsc.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:26 +08:00
Yonghua Huang
316731c9a5 hv: pass-through xsave feature to guests
enable Xsave feature and pass-through it to guests
 update based on v2:
  - enable host xsave before expose it to guests.
  - add validation for the value to be set to 'xcr0' before call xsetbv
    when handling xsetbv vmexit.
  - tested in SOS guest, created two threads to do different
    FP calculations,test code runs in user land of sos.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:23 +08:00
Li, Fei1
6c1122f869 cpuid restruct
Generate all common virtual cpuid entries for flexible support of
guest VCPUID emulation, by decoupling from PCPUID.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Chen, Jason CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:38 +08:00
Yonghua Huang
d6904b412c hv: rename VM exit handlers in vlapic
to keep aligned with the vmexit reasons' name defined in
SPEC.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:37 +08:00
Yonghua Huang
7d8803f5ea hv:enable APICv features based on CPU capability
this patch is to detect and enable only APICv features which
are actually supported by the processor, instead fo tuning on
all features by default.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:37 +08:00
Yonghua Huang
f01a8eef58 Add APIC ACCESS VMexit handler
Update 'apic_access_exit_handler()' function to emulate
guest instruments to read/write guest's lapic registers page

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:37 +08:00
Yonghua Huang
83e78e16c7 align the coding style when access VMEXIT_QUAL
- align coding style to avoid redundant operations
   when operating on reading  VMX_EXIT_QUALIFICATION

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:36 +08:00
Eddie Dong
7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00