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53 Commits

Author SHA1 Message Date
Yonghua Huang
7d8803f5ea hv:enable APICv features based on CPU capability 
this patch is to detect and enable only APICv features which
are actually supported by the processor, instead fo tuning on
all features by default.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
 2018-05-15 17:19:37 +08:00
Mingqiang Chi
35f5eef658 Add page mask MACRO 
Add 'CPU_PAGE_MASK' used for calculate address,
Change IA32E_REF_MASK from 0x7ffffffffffff000 to 0x000ffffffffff000
for MMU/EPT entry, bit62:52(ignore) bit63(VE/XD)
if we want to obtain the address from the MMU/EPT entry,need to clear
bit63:52 by IA32E_REF_MASK

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
 2018-05-15 17:19:37 +08:00
Eddie Dong
7a3a539b17 initial import 
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
 2018-05-11 14:44:28 +08:00